Flipped VFET Gate Length Control via Self-Aligned Inner Spacers
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Solution Overview
Problem
In vertical field effect transistors (VFETs), controlling the gate length is challenging due to the inapplicability of traditional lithography or sidewall image transfer processes, which affects leakage, drive current, and speed.
Innovation Solution
The method involves forming a vertical channel layer with inner spacers on opposite ends to determine the gate length, sandwiching the channel layer between sacrificial layers, recessing the sides, and growing epitaxial source or drain regions, followed by rotating the device to create self-aligned junctions and a controlled gate length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional lithography or sidewall image transfer processes are used to control gate length, then manufacturing precision is improved, but these processes are not applicable to VFET structures
Solution Approach 1:
Instead of forming the gate first and then defining its length through lithography, the patent inverts the sequence by first forming sacrificial layers that define the future gate length, then growing the gate stack between them. This allows the gate length to be defined by the sacrificial layer dimensions rather than by lithography patterns applied to the gate itself.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that temporarily occupy the space where the gate will eventually be formed. These sacrificial layers serve as placeholders that define the gate length and are later removed, enabling precise gate length control without requiring direct lithography on the gate structure.
2Device complexity
If gate length is not precisely controlled, then device performance is improved in terms of simplicity, but leakage, drive current, and speed are adversely affected
Solution Approach 1:
The patent performs preliminary action by forming the sacrificial layers before forming the gate stack. The sacrificial layers are pre-positioned to define the exact gate length, ensuring that when the gate is formed between them, the gate length is precisely controlled without requiring complex post-processing adjustments.
Solution Approach 2:
The sacrificial layers self-align with the channel structure through the epitaxial growth process, automatically defining the gate length based on the channel dimensions. This self-alignment mechanism eliminates the need for additional alignment steps and complex control processes, achieving precise gate length control through the structure's own geometry.
3Manufacturing precision
If self-aligned junctions are formed, then manufacturing precision is improved, but device complexity increases due to additional process steps
Solution Approach 1:
The patent merges multiple functions into the sacrificial layer structure: it serves as a placeholder for gate length definition, a self-alignment reference for the gate stack, and a template for source/drain region formation. By combining these functions into a single structural element, the process achieves self-aligned junctions without proportionally increasing complexity.
Solution Approach 2:
The sacrificial layers perform multiple functions throughout the fabrication process: defining gate length, enabling self-aligned gate formation, and serving as templates for source/drain regions. This multi-functionality reduces the need for separate alignment structures and processes, balancing the achievement of self-aligned junctions with manageable process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables self-aligned junctions, reduces cell area, minimizes parasitic capacitance, and improves contact resistance, resulting in enhanced performance and control over gate length in VFETs.
Implementation Method 1
epitaxially growing a first epitaxial source or drain (S/D) region on one end of the vertical channel layer
Data Source
AI summary
A technique relates to a semiconductor device. A vertical channel layer is formed with inner spacers on opposite ends of the vertical channel layer. A gate stack is formed having a gate length determined by the inner spacers. Source or drain (S/D) regions are formed on the opposite ends of the vertical channel layer.