Multi-Voltage Flit Receivers for Lane Error Correlation Control
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Solution Overview
Problem
As data rates in serial interconnects increase, maintaining a bit error rate (BER) of 10−12 or better becomes challenging due to cross-talk, inter-symbol interference, and channel loss, especially with the deployment of PAM-4 encoding for next-generation data rates like PCIe Gen 6, where the target BER is higher at 10−6.
Innovation Solution
The implementation of mechanisms and logic circuitry to address error bursts on each lane and across lanes, including the evaluation of error correlation to tune circuits or deploy appropriate Forward Error Correction (FEC) techniques, such as interleaved Error Correcting Code (ECC) groups and Cyclic Redundancy Check (CRC).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rates in serial interconnects are increased to achieve higher productivity, then productivity is improved, but bit error rate deteriorates due to cross-talk, inter-symbol interference, and channel loss
Solution Approach 1:
The patent divides error correction into multiple stages using different FEC schemes. A first FEC scheme handles dominant error sources, while a second FEC scheme addresses remaining errors. This segmentation of error correction functions allows the system to maintain high data rates while achieving the required BER performance through coordinated multi-stage correction.
Solution Approach 2:
The patent dynamically adjusts equalization parameters and FEC configuration based on channel conditions. By monitoring error patterns and channel characteristics, the system modifies equalization settings and selects appropriate FEC schemes, enabling adaptation to varying channel quality while maintaining high data rates and acceptable BER performance.
2Productivity
If PAM-4 encoding is deployed to achieve higher data rates, then productivity is improved, but reliability deteriorates with a higher target BER of 10^-6
Solution Approach 1:
The patent employs a two-stage FEC architecture where the first FEC scheme (such as LDPC) corrects the majority of errors introduced by PAM-4 encoding and channel impairments. The second FEC scheme (such as BCH or RS) provides additional correction for residual errors. This segmented approach enables PAM-4 to achieve its high data rate potential while meeting the relaxed BER target of 10^-6.
Solution Approach 2:
The patent combines multiple FEC technologies (e.g., LDPC and BCH, or Reed-Solomon and convolutional codes) into a hybrid error correction system. This composite FEC approach leverages the strengths of different coding schemes to achieve superior error correction performance, enabling reliable PAM-4 operation at high data rates with BER target of 10^-6.
3Reliability
If the number of lanes is increased to maintain BER performance, then reliability is improved, but device complexity increases due to cross-talk and inter-symbol interference
Solution Approach 1:
The patent implements feedback mechanisms where error statistics and channel characteristics are monitored and used to adjust equalization parameters and FEC configuration. This feedback loop enables the system to optimize performance across multiple lanes by adapting to cross-talk and ISI conditions, maintaining BER performance without requiring excessive lane multiplication.
Solution Approach 2:
The patent employs dynamic equalization and adaptive FEC selection that responds to real-time channel conditions. By continuously adjusting equalization settings and FEC parameters based on observed error patterns, the system can maintain reliable operation across multiple lanes without requiring static over-provisioning, thereby managing device complexity while preserving BER performance.
Data Source
AI summary
Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.