FLL and LDO Circuit Control With Switched-Capacitor Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Frequency Lock Loop (FLL) circuits and Low-Dropout (LDO) regulators face challenges with large passive filtering components that increase silicon area usage and cause slow loop responses and frequency fluctuations, while comparator-based current limits in LDOs lead to unstable control and voltage spikes during transitions.
Innovation Solution
The implementation of FLL circuits with switched capacitor circuits to reduce the number of filtering components, and the use of a ratio-based current-sensing loop with frequency compensation in LDOs to achieve stable and predictable power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If large passive filtering components are used in FLL circuits, then frequency stability is improved, but silicon area usage increases and loop response becomes slow
Solution Approach 1:
The patent changes the parameters of the filtering components by using switched capacitor circuits with specific capacitance values (e.g., 0.5pF to 2pF) and switching frequencies (e.g., 100kHz to 1MHz) to achieve the required frequency stability with much smaller area compared to traditional large passive components
Solution Approach 2:
The patent replaces traditional mechanical/passive filtering components (large inductors and capacitors) with electronic switched capacitor circuits that use MOSFET switches and small capacitors, substituting a bulky passive system with a compact active electronic system
2Stability of the object's composition
If large passive filtering components are used in FLL circuits, then frequency stability is improved, but loop response speed decreases
Solution Approach 1:
The patent optimizes the parameters of the switched capacitor circuit including capacitance values, switching frequencies, and resistance values to achieve a balance where the loop responds quickly to frequency changes while maintaining stability through the feedback mechanism
3Use of energy by moving object
If comparator-based current limits are used in LDOs, then power consumption is reduced, but control stability deteriorates and voltage spikes occur during transitions
Solution Approach 1:
The patent implements a feedback mechanism using a sense amplifier that continuously monitors the voltage difference between the main regulation loop output and the current limit loop output, providing smooth transition control that maintains stability while managing power consumption during limit mode operation
Solution Approach 2:
The patent creates a dynamic control system where the sense amplifier's output voltage dynamically adjusts during transitions between normal and limit modes, enabling smooth handoff between control loops and preventing abrupt voltage spikes while maintaining appropriate power consumption levels
Data Source
AI summary
Frequency lock loop (FLL) circuits, low voltage dropout regulator circuits, and related methods are disclosed. An example gate driver integrated circuit includes a first die including a FLL circuit to generate a first clock signal having a first phase and a first frequency, a second clock signal having the first frequency and a second phase different from the first phase, and control a plurality of switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency, and a second die coupled to the first die, the second die including a low dropout (LDO) circuit and a driver, the driver configured to control a transistor based on the first frequency, the second die configured to be coupled to the transistor, the LDO circuit to generate a pass-gate voltage based on an output current of the LDO circuit satisfying a current threshold.