Frequency-Locked Loop Logic for Temperature-Stable Oscillator Calibration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Relaxation oscillators in integrated circuits are vulnerable to temperature changes, causing frequency instability due to the temperature-dependent resistance of resistive elements, which can lead to system failures.
Innovation Solution
A frequency-locked loop (FLL) logic circuit is implemented, comprising a validity signal generator, clock divider, synchronizer, clock counter, and code limiter, which receives an external clock signal, determines glitches, generates a reference frequency, synchronizes oscillator phases, counts pulses, and adjusts frequency selection values to calibrate the oscillation frequency, ensuring stability across temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a relaxation oscillator is used as a clock source, then cost is reduced and power consumption is lowered, but frequency stability deteriorates due to temperature changes
Solution Approach 1:
The patent uses a frequency-locked loop (FLL) that dynamically adjusts the frequency selection value based on temperature changes. The system measures the oscillation frequency, compares it with a target frequency, and modifies the frequency selection signal to compensate for temperature-induced drift, thereby maintaining frequency stability without requiring a completely different oscillator design
Solution Approach 2:
The patent implements a feedback mechanism where the oscillation frequency is continuously monitored by a frequency counter, compared with the target frequency, and the difference is used to adjust the frequency selection value. This closed-loop feedback system automatically corrects frequency deviations caused by temperature variations, resolving the contradiction between simplicity and stability
2Measurement precision
If frequency calibration is performed continuously, then frequency accuracy is improved, but power consumption increases
Solution Approach 1:
The patent performs frequency calibration periodically rather than continuously. The FLL logic circuit activates the frequency measurement and adjustment process at specific intervals or under specific conditions (such as when temperature change is detected), thereby maintaining frequency accuracy while significantly reducing power consumption compared to continuous calibration
Data Source
AI summary
A frequency-locked loop (FLL) logic circuit, including a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator; a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal; a clock counter configured to count a number of pulses of the oscillator clock signal during a reference time; and a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.