FLL Oscillator Clock Using Switched-Capacitor Divider for Low-EMI Locking
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Solution Overview
Problem
Existing frequency locked loop (FLL) oscillators face challenges in minimizing area and power consumption while maintaining performance, particularly in high-frequency applications where phase noise and frequency variation are tolerable, such as in OOK-based transmission systems and clocked power converters, and require innovative designs to mitigate electromagnetic interference (EMI).
Innovation Solution
The implementation of a free-running FLL oscillator with a switched capacitor resistive divider and spread spectrum clocking, utilizing a switched-capacitor resistor-divider and RC relaxation oscillator to generate a frequency control signal and modulate the oscillator signal with spread spectrum modulation, effectively reducing EMI and frequency variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL (phase locked loop) is used to generate a clock signal, then frequency stability and phase noise performance are improved, but area and power consumption increase significantly
Solution Approach 1:
The patent extracts the phase detection function from the complete PLL system, using only the VCO and frequency detection components necessary for the application. This selective extraction maintains adequate frequency stability while removing unnecessary circuitry that would increase area and power consumption.
Solution Approach 2:
The patent changes the control parameter from phase (as in traditional PLLs) to frequency detection using a frequency-to-voltage converter. This parameter change allows the system to achieve sufficient frequency stability through frequency locking rather than phase locking, reducing the complexity and size of the control loop.
2Reliability
If a PLL is used to generate a clock signal, then frequency stability and phase noise performance are improved, but power consumption increases
Solution Approach 1:
The patent removes the phase detector and associated control logic from the traditional PLL architecture, retaining only the essential VCO and frequency detection components. This extraction maintains frequency stability while significantly reducing the number of active components that consume power.
Solution Approach 2:
The frequency-to-voltage converter automatically generates the control signal based on the VCO output frequency, eliminating the need for complex external control logic. The system self-regulates frequency stability through this automatic frequency detection and control mechanism, reducing power consumption.
3Object-generated harmful factors
If spread spectrum modulation is applied to reduce EMI, then electromagnetic interference is reduced, but frequency variation increases
Solution Approach 1:
The patent implements dynamic frequency modulation through spread spectrum techniques, where the carrier frequency is intentionally varied according to a predetermined pattern. This dynamic frequency variation spreads the EMI energy across a broader spectrum while the FLL control loop maintains the average frequency stability.
Solution Approach 2:
The frequency-locked loop provides continuous feedback control that monitors the VCO output frequency and adjusts the control voltage to maintain the center frequency. This feedback mechanism ensures that while instantaneous frequency varies for EMI reduction, the average frequency remains stable within acceptable tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a compact, low-power FLL oscillator that maintains frequency stability across process, voltage, and temperature (PVT) variations, reducing EMI and enabling efficient operation in high-frequency applications with improved noise rejection and reduced frequency variation.
Implementation Method 1
a switched-capacitor resistor-divider including a resistor and a switched capacitor coupled at an R-divider node by switching the switching capacitor in response the FLL_clk to convert the frequency fosc to a switched-capac resistance
Implementation Method 2
providing a negative feedback RC transition voltage to the inverting input of the comparator, based on an RC circuit characterized by an RC time constant
Implementation Method 3
generating a tripping threshold voltage by switching between a VTH upper tripping threshold voltage, and a VTL lower tripping threshold voltage, with switching controlled by the comparator output
Data Source
Figure 1
Figure 2A
Figure 2B~2D
AI summary
In described examples, an FLL (frequency locked loop) oscillator/clock generator (100) includes a free-running oscillator (110), which generates an FLL clk with an FLL-controlled frequency fosc- The FLL control loop includes a switched capacitor resistor divider (130) that converts fosc to a resistance, generating an FLL feedback voltage (Vfosc) to generate a loop control signal (OSC cntrl) input to the oscillator (110). In response, the oscillator frequency locks FLL clk to fosc. In an example implementation, the FLL oscillator/clock generator (100) operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.