FLL Oscillator Clock Using Switched-Capacitor Feedback for PVT Stability
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Solution Overview
Problem
Existing frequency locked loop (FLL) oscillators require external components and suffer from significant frequency variation due to process voltage temperature (PVT) changes, which affects the stability and noise rejection in high-frequency applications like OOK-based transmission and clocked power converters.
Innovation Solution
The implementation of a free-running FLL oscillator circuit with a switched-capacitor resistive divider and spread spectrum clocking, which generates a frequency-locked clock signal with spread spectrum modulation, reducing frequency variation and electromagnetic interference (EMI) by using a switched capacitor to convert frequency to resistance and incorporating a comparator with tripping threshold voltages for triangular modulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a free-running oscillator is used in an FLL to avoid PLL reference clock requirements, then area and power consumption are reduced, but frequency stability deteriorates due to significant frequency variation from PVT changes
Solution Approach 1:
The patent implements an FLL control loop that continuously monitors the oscillator output frequency and adjusts the oscillator control signal to maintain the desired frequency. The feedback mechanism includes a frequency detector that compares the actual oscillator frequency with the target frequency and generates a control signal to correct frequency deviations caused by PVT variations, thereby maintaining frequency stability while using a power-efficient free-running oscillator architecture
Solution Approach 2:
The patent employs a switched-capacitor resistive divider that dynamically adjusts resistance values based on detected frequency deviations. By changing the resistance parameter in real-time according to the frequency error signal, the system compensates for PVT-induced frequency variations and maintains stable oscillation frequency without requiring external components
2Reliability
If external components are used in traditional FLL oscillators, then frequency stability can be improved, but device complexity and area increase
Solution Approach 1:
The patent integrates the frequency detection, control signal generation, and frequency adjustment functions into a unified FLL control loop architecture. The switched-capacitor resistive divider combines resistance adjustment and frequency control functions in a single integrated circuit block, eliminating the need for external components while maintaining frequency stability through internal feedback mechanisms
3Object-generated harmful factors
If spread spectrum modulation is applied to reduce EMI, then electromagnetic interference is reduced, but frequency control complexity increases
Solution Approach 1:
The patent implements spread spectrum modulation by periodically varying the oscillator frequency around its center frequency according to a predetermined modulation pattern. This periodic frequency deviation spreads the EMI energy across a broader frequency spectrum, reducing peak EMI emissions. The modulation is achieved through periodic adjustment of the oscillator control signal within the existing FLL framework, leveraging the same feedback mechanism without requiring separate complex modulation circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces frequency variation across PVT changes, enhances noise rejection, and allows for efficient spread spectrum control, enabling better frequency stability and reduced EMI in high-frequency applications without the need for external components.
Implementation Method 1
switching the switching capacitor in response the FLL_clk to convert the frequency fosc to a switched-capac resistance
Implementation Method 2
providing a negative feedback RC transition voltage to the inverting input of the comparator, based on an RC circuit characterized by an RC time constant
Implementation Method 3
outputting the frequency control signal from the R-divider node based on voltage division provided by the resistor and the switched-capac resistance
Implementation Method 4
generating a tripping threshold voltage by switching between a VTH upper tripping threshold voltage, and a VTL lower tripping threshold voltage, with switching controlled by the comparator output
Data Source
AI summary
An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an FLL-controlled frequency fOSC. The FLL control loop includes a switched capacitor resistor divider that converts fOSC to a resistance, generating an FLL feedback voltage Vfosc used to generate a loop control signal OSC_cntrl input to the oscillator. In response, the oscillator frequency locks FLL_clk to fosc. In an example implementation, the FLL oscillator/clock operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.