Frequency Locked Loop Preset for Fast PLL Lock Time
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Solution Overview
Problem
Phase locked loop (PLL) circuits take too long to achieve lock when multiplying a low reference frequency to a high output frequency, which is undesirable for applications requiring fast wake-up times.
Innovation Solution
A digital frequency locked loop (FLL) with a lower loop divider value is used to quickly set the controllable oscillator of the PLL to the desired output frequency, allowing the PLL to lock more rapidly by generating an intermediate signal and adjusting the division factor to achieve the desired output frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a phase locked loop multiplies a low reference frequency to a high output frequency, then the desired output frequency is achieved, but the lock time becomes too long (about 1 millisecond)
Solution Approach 1:
The patent applies preliminary action by using a frequency locked loop (FLL) to pre-set the controllable oscillator to the desired output frequency before the phase locked loop (PLL) is activated. This preliminary frequency setting reduces the time required for the PLL to achieve lock, thereby decreasing the overall wake-up time while maintaining the ability to generate the desired high output frequency from a low reference frequency.
2Speed
If a high loop divider value is used to multiply frequency, then the desired output frequency is achieved, but the lock time increases significantly
Solution Approach 1:
The patent uses an intermediary approach by introducing a frequency locked loop (FLL) with a lower loop divider value as a mediator. The FLL quickly sets the controllable oscillator to the target frequency, and then transfers control to the PLL. This intermediary FLL stage enables fast initial frequency setting, after which the PLL maintains the desired frequency multiplication with its higher loop divider value, thus combining the advantages of both approaches.
Data Source
AI summary
A method of quickly locking a locked loop includes generating an intermediate reference signal having an intermediate reference frequency between a desired output frequency and a reference frequency of a reference signal, and setting an output frequency of a controllable oscillator to the desired output frequency using a first locked loop having a first loop divider value. The first loop divider value is set such that the intermediate reference frequency multiplied by the first loop divider value is equal to the desired output frequency. The controllable oscillator is then coupled to a second locked loop when the first locked loop locks, with the second locked loop is being activated. The first locked loop is then deactivated.