Frequency-Locked Loop Resynchronization for Faster Frequency Tracking
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Solution Overview
Problem
Frequency locked loops (FLLs) with digitally controlled oscillators face increased iteration times and response delays when varying clock frequency and supply voltage, leading to slower reaction times.
Innovation Solution
A frequency locked loop design that includes a digitally controlled oscillator, a frequency counter and sequencer circuit, and a controller with a variable frequency clock signal, utilizing a resynchronization circuit and trigger signal to synchronize phases and reduce iteration time by allowing the counting phase to start earlier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency and supply voltage are increased to improve processing speed, then the iteration time of the FLL must be significantly increased to accommodate the permitted variations, but this leads to an increased response time of the FLL
Solution Approach 1:
The resynchronization circuit performs preliminary alignment of the trigger signal with the reference clock signal before the trigger signal is used to control the frequency counter. This preliminary action ensures that the trigger signal is properly synchronized without requiring additional time during the critical measurement phase, thereby reducing the overall iteration time while maintaining processing speed.
Solution Approach 2:
The resynchronization circuit acts as an intermediary between the trigger signal and the frequency counter, mediating the timing relationship between these two components. By introducing this intermediate stage, the system can accommodate variable clock frequencies and supply voltages without directly impacting the iteration time, thus resolving the contradiction between processing speed and response time.
2Adaptability or versatility
If the iteration time is increased to accommodate variations in supply voltage and clock frequency, then the FLL can maintain correct operation under varying conditions, but the response time of the FLL increases
Solution Approach 1:
The system dynamically adjusts its operation by using a resynchronization circuit that can adapt to varying clock frequencies and supply voltages. The resynchronization circuit dynamically aligns the trigger signal with the reference clock signal, allowing the FLL to maintain correct operation under varying conditions without requiring a fixed, conservative iteration time that would slow down the response.
Solution Approach 2:
The invention changes the timing parameters of the system by introducing a resynchronization stage that independently handles the alignment of signals. This parameter change allows the system to operate correctly across a range of supply voltages and clock frequencies while maintaining a consistent and optimized iteration time, thus improving both adaptability and response time.
3Measurement precision
If the counting phase is extended to ensure accurate frequency estimation, then the measurement precision is improved, but the iteration period increases
Solution Approach 1:
The resynchronization circuit performs preliminary alignment of the trigger signal before the counting phase begins. This preliminary action ensures that the frequency counter starts counting at the optimal moment, maximizing the use of available time during the counting phase. As a result, accurate frequency estimation can be achieved without extending the iteration period, as the effective measurement time is optimized through proper synchronization.
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C~3D
AI summary
The invention concerns a frequency locked loop comprising: a digitally controlled oscillator (102) configured to generate a frequency signal (F); a frequency counter (310) configured to generate an estimate (f EST) of the frequency of the frequency signal based on a reference clock signal (CLK_REF); and a controller (314) configured to generate a digital control signal (C_FREQ) for controlling the digitally controlled oscillator based on the estimated frequency, wherein the controller is clocked by a further clock signal (CLK) having a variable frequency, and the controller is configured to generate a trigger signal (AUTO_CLEAR) for triggering a counting phase of the frequency counter.