Frequency Locked Loop State Restore for Fast Relocking
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Solution Overview
Problem
Frequency locked loops (FLLs) experience significant lock time delays when re-enabled after being disabled, which can lead to increased power consumption and processing delays in applications like packet data processing in transceivers.
Innovation Solution
Storing the state of the FLL when it is locked onto a reference signal and initializing the loop with this stored state upon re-enablement, allowing the FLL to rapidly relock and minimize relocking time, enabling immediate use of the output clock signal without waiting for locking to occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the FLL is disabled and then re-enabled, then power consumption is reduced during idle periods, but the relocking time increases significantly causing processing delays
Solution Approach 1:
The patent stores the FLL state (including phase detector output, charge pump state, and VCO control voltage) in memory before disabling the loop. Upon re-enablement, this pre-stored state is restored to initialize the FLL, allowing it to skip the lengthy acquisition phase and relock rapidly within one or two reference clock cycles instead of requiring a complete reacquisition sequence.
2Productivity
If the FLL relocks slowly after re-enablement, then processing of packet data is delayed, but faster relocking requires additional circuitry and complexity
Solution Approach 1:
The patent creates a digital copy of the FLL state parameters and stores them in memory. This copy can be rapidly restored without requiring complex analog circuitry or additional hardware components. The stored state values are simply written back to the respective registers and control elements, achieving fast relocking through simple digital storage and retrieval operations rather than complex re-synchronization circuitry.
3Loss of time
If the FLL state is stored and restored, then relocking time is reduced to one or two cycles, but memory storage and state management are required
Solution Approach 1:
The FLL state is segmented into discrete, independently storable parameters including the phase detector output value, charge pump control state, and VCO control voltage. Each parameter is stored in a separate memory location or register, allowing for systematic retrieval and restoration. This segmentation transforms the complex continuous state into manageable discrete values that can be efficiently stored and restored without requiring complex memory management.
Data Source
AI summary
An apparatus includes a frequency locked loop and a controller. The controller stores a state of the frequency locked loop at which an output signal of the frequency locked loop is locked onto a reference signal and subsequently initializes the frequency locked loop with the stored state to cause the frequency locked loop to relock the output signal to the reference signal.