Frequency-Locked Loop Switching Circuit for Low-Jitter Clock Stability
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Solution Overview
Problem
Frequency locked loop circuits in electronic products often introduce noise into clock signals, leading to instability and jitter, which existing solutions fail to adequately address.
Innovation Solution
A frequency locked loop circuit comprising a frequency generation circuit, impedance circuits, and a switching circuit that periodically switches the terminals between impedance nodes to adjust impedance values based on the output clock signal, utilizing a chopper operational amplifier and low-frequency pass filter to modulate and filter out noise, thereby reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a frequency locked loop circuit is applied to generate clock signals, then the clock signal can be generated, but noise is introduced causing jitter and instability
Solution Approach 1:
The patent applies periodic switching action by periodically switching the connection between the operational amplifier and the impedance circuits based on the clock signal phases. This periodic switching modulates the low-frequency noise to high-frequency regions where it can be filtered out, thereby reducing noise-induced jitter while maintaining clock signal stability
Solution Approach 2:
The patent introduces impedance circuits as intermediary elements between the operational amplifier and the clock signal generation path. These impedance circuits, when periodically switched, act as mediators that transform the noise spectrum from low-frequency (harmful) to high-frequency (filterable), thus eliminating the harmful noise effect
2Reliability
If impedance circuits are added to reduce noise, then noise-induced jitter is reduced, but circuit complexity increases
Solution Approach 1:
The impedance circuits are designed to serve multiple functions: they provide noise filtering through periodic switching, maintain signal integrity, and work in conjunction with the existing operational amplifier. This multi-functionality reduces the need for additional separate noise filtering components, thereby limiting the increase in circuit complexity
Data Source
AI summary
A frequency locked loop circuit, including a frequency generation circuit, a first impedance circuit, a second impedance circuit and a switching circuit. The frequency generation circuit includes a positive terminal and a negative terminal. The frequency generation circuit outputs an output clock signal according to a voltage difference between the positive terminal and the negative terminal. The first impedance circuit and the second impedance circuit are electrically coupled to a first impedance node and a second impedance node, respectively. The second impedance circuit adjusts an impedance value of the second impedance circuit according to the output clock signal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node.