Fractional Logarithmic Number System Adder Circuit
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Solution Overview
Problem
Existing methods for adding fractional logarithmic number system (FLNS) operands are inefficient due to the need for conversion to fixed point format, which increases hardware resource requirements and degrades performance in applications like neural networks.
Innovation Solution
A conversion-free FLNS adder circuit that performs addition by using a compare-and-swap circuit, subtraction circuit, approximation circuit, and summing circuit to calculate the sum of FLNS operands without converting them to fixed point, thereby reducing resource requirements and improving computational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conversion to fixed point format is used for adding FLNS operands, then addition can be performed using standard arithmetic circuits, but hardware resource requirements increase and performance degrades
Solution Approach 1:
The patent changes the parameter representation from fixed point to fractional logarithmic number system (FLNS), where numbers are represented as (sign, exponent, mantissa) tuples. This parameter change allows addition to be performed directly in FLNS format using the formula: a + b = sign(a) * 2^exp(a) * (1 + mantissa(a)/2^w) + sign(b) * 2^exp(b) * (1 + mantissa(b)/2^w), eliminating the need for conversion to fixed point format and reducing hardware resource requirements.
2Ease of manufacture
If conversion to fixed point format is used for adding FLNS operands, then standard arithmetic circuits can be used, but computational efficiency decreases
Solution Approach 1:
The patent changes the parameter representation from fixed point to fractional logarithmic number system (FLNS), where numbers are represented as (sign, exponent, mantissa) tuples. This parameter change allows addition to be performed directly in FLNS format using the formula: a + b = sign(a) * 2^exp(a) * (1 + mantissa(a)/2^w) + sign(b) * 2^exp(b) * (1 + mantissa(b)/2^w), eliminating the need for conversion to fixed point format and reducing hardware resource requirements.
3Ease of operation
If lookup tables are used for addition in LNS, then addition can be performed, but memory requirements significantly increase
Solution Approach 1:
The patent changes the parameter representation from standard LNS to fractional LNS (FLNS), representing numbers as (sign, exponent, mantissa) where the mantissa is a fixed-width integer. This enables direct algebraic addition using the formula involving sign bits, exponents, and mantissas, eliminating the need for large lookup tables and significantly reducing memory requirements while maintaining addition capability.
Data Source
AI summary
An adder for fractional logarithmic number system (FLNS) format operands includes a compare-and-swap circuit that inputs first and second FLNS operands represented by fixed point values and provides a greater one as operand x and a lesser or equal one as operand y. Sign bits are sx and sy of x and y, respectively, qx and qy, are integer portions of x and y, respectively, fraction portions of x and y have integer values rx and ry, respectively. The compare-and-swap circuit is configured to provide sx as a sign bit, sz of a sum z=x(1+y/x) for x≠0. A subtraction circuit subtracts (qy+ry/n)−(qx+rx/n) and outputs qα and rα, such that α=y/x, where n=2w<sub2>r </sub2>and wr is a bit-width of rx and ry. An approximation circuit provides an approximation of (1+α) to a nearest FLNS value, β, as fixed point value having an integer portion qβ and a fraction portion that has an integer value rβ. A summing circuit adds qx+rx/n+qβ+rβ/n in response to sx=sy, and subtracts qx+rx/n−qβ−rβ/n in response to sx≠sy, to provide the sum as a fixed point value having an integer portion qz and a fraction portion that as an integer has a value rz.