Floating-Point Accumulation via Convert-and-Accumulate Instruction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Floating-point arithmetic calculations are non-associative, leading to reproducibility issues and slowness due to rounding and normalization during accumulation, making it necessary to perform operations sequentially.

Innovation Solution

The implementation of a convert and accumulate instruction that converts floating-point operands into N-bit fixed-point operands, allowing for associative accumulation within a P-bit fixed-point representation, reducing the risk of overflow and enabling parallelization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If floating-point accumulation is performed sequentially to ensure reproducibility, then result accuracy is improved, but processing speed deteriorates

Engineering Contradiction:
Improveresult accuracyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent changes the numerical representation parameter from floating-point to fixed-point format. By converting floating-point numbers to fixed-point representation with sufficient precision (P bits where P ≥ N + log2(K)), the system achieves both reproducibility (through exact arithmetic) and improved performance (through parallel processing capability). This parameter transformation resolves the contradiction by eliminating rounding errors while enabling vectorized operations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces fixed-point representation as an intermediary form between floating-point input and floating-point output. The conversion process (floating-point → fixed-point for accumulation → floating-point) acts as a mediator that preserves precision during accumulation while enabling efficient parallel computation, thus resolving the speed-accuracy tradeoff.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If floating-point operations include rounding and normalization, then representation flexibility is improved, but computational complexity worsens

Engineering Contradiction:
Improverepresentation flexibilityVSAvoidcomputational complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts the problematic rounding and normalization operations from the accumulation process by using fixed-point representation. Fixed-point arithmetic eliminates the need for dynamic range adjustment and rounding during accumulation, simplifying the computational logic while maintaining sufficient precision through appropriate bit allocation (P bits for K numbers with N fraction bits each).

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If floating-point accumulation maintains full precision, then measurement accuracy is improved, but overflow risk worsens

Engineering Contradiction:
Improvemeasurement accuracyVSAvoidoverflow risk
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent transitions from the floating-point dimension (which handles range through exponentiation but loses precision through rounding) to the fixed-point dimension (which handles precision through dedicated fraction bits and manages range through sufficient total bit width). By allocating P bits where P ≥ N + log2(K), the system simultaneously achieves full precision retention and overflow prevention through dimensional transformation of the numerical representation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10216479B2Apparatus and method for performing arithmetic operations to accumulate floating-point numbers
Publication Date: 2019.02.26 ARM LTD
  • US10216479B2 patent drawing
  • US10216479B2 patent drawing
  • US10216479B2 patent drawing

AI summary

An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding the convert and accumulate instruction to generate one or more control signals to control the execution circuitry to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand. The execution circuitry accumulates each corresponding N bit fixed-point operand and a P bit fixed-point operand identified by the convert and accumulate instruction in order to generate a P bit fixed-point result value, where P is greater than N and also has M fraction bits.