Floating Base Vertical BJT for Low Clamping Voltage ESD Protection
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Solution Overview
Problem
Existing vertical transient voltage suppressors have high clamping voltage and compromised ESD performance due to a grounded base of the bipolar junction transistor, which limits their effectiveness in protecting electronic devices from electrostatic discharge.
Innovation Solution
The base of the vertical bipolar junction transistor is floated to maintain a low holding voltage and clamping voltage, enhancing ESD performance by incorporating a diode and heavily-doped areas in a semiconductor substrate with specific conductivity types and epitaxial layers, allowing for efficient energy dissipation during ESD events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the base of the bipolar junction transistor is grounded to limit the gain, then the stability is improved, but the clamping voltage increases and ESD performance deteriorates
Solution Approach 1:
The patent inverts the conventional grounding approach by floating the base of the bipolar junction transistor instead of grounding it. This inversion allows the base potential to be dynamically controlled through the diode connection, achieving both stability and superior ESD performance. The base is connected to the cathode of a diode whose anode is connected to the heavily-doped n-type area, creating a feedback mechanism that maintains stable operation while enabling low clamping voltage.
2Power
If the base of the bipolar junction transistor is grounded, then the gain is limited, but the holding voltage increases
Solution Approach 1:
The patent introduces a diode as an intermediary element between the base and the heavily-doped n-type area. This diode acts as a mediator that controls the base potential, allowing the transistor to maintain appropriate gain while keeping the holding voltage low. The diode's forward voltage drop provides a natural reference that prevents the base potential from rising too high, thereby maintaining low holding voltage without sacrificing gain.
3Device complexity
If the base of the bipolar junction transistor is grounded, then the circuit complexity is reduced, but the clamping voltage increases
Solution Approach 1:
The patent achieves multi-functionality by having the diode serve multiple purposes: it controls the base potential, provides a reference voltage, and enables low clamping voltage operation. The heavily-doped n-type area also serves dual functions as both the collector region and the connection point for the diode. This multi-functional design maintains relatively simple circuit structure while achieving superior ESD performance with low clamping voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces impedance and enhances ESD performance by maintaining low holding and clamping voltages, effectively protecting electronic devices from electrostatic discharge.
Implementation Method 1
a diode (22) arranged in the semiconductor substrate (14) and electrically connected to the second heavily-doped area (20) through a conductive trace (24)
Implementation Method 2
the first doped well (16), the first heavily-doped area (18), and the semiconductor substrate (14) form a vertical bipolar junction transistor (BJT) (32)
Implementation Method 3
the P-type heavily doped area (19) and the second N-type heavily-doped area (20) form a Zener diode
Data Source
AI summary
A vertical transient voltage suppression device includes a semiconductor substrate having a first conductivity type, a first doped well having a second conductivity type, a first heavily-doped area having the first conductivity type, a second heavily-doped area having the first conductivity type, and a diode. The first doped well is arranged in the semiconductor substrate and spaced from the bottom of the semiconductor substrate, and the first doped well is floating. The first heavily-doped area is arranged in the first doped well. The second heavily-doped area is arranged in the semiconductor substrate. The diode is arranged in the semiconductor substrate and electrically connected to the second heavily-doped area through a conductive trace.