Floating Bit Line Programming for Flash Memory Coupling
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Solution Overview
Problem
As memory devices become smaller, capacitive coupling effects during programming become more problematic, leading to unintended raising of the floating gate potential in nearby storage elements, which affects the accuracy and efficiency of programming in multi-state flash memory devices.
Innovation Solution
The solution involves allowing the channel of the storage element still being programmed to float at a potential that slows down programming without fully inhibiting it, thereby reducing capacitive coupling while enabling partial speed programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bit line is grounded during programming to inject electrons into the floating gate, then programming efficiency is improved, but capacitive coupling effects raise the channel potential in nearby storage elements, causing unintended floating gate potential changes and reducing programming accuracy
Solution Approach 1:
The patent applies dynamics by transitioning the bit line from a static grounded state to a dynamic floating state during programming operations. The bit line potential is allowed to float rather than being fixed at ground, enabling it to adaptively respond to capacitive coupling effects from neighboring storage elements. This dynamic adjustment prevents unintended floating gate potential changes while maintaining programming efficiency.
Solution Approach 2:
The patent changes the electrical parameter of the bit line from a fixed ground potential (0V) to a floating potential that can vary during programming. This parameter change allows the bit line to compensate for capacitive coupling effects by adjusting its potential state, thereby improving programming accuracy without sacrificing efficiency.
2Volume of moving object
If memory devices are scaled down to reduce size, then device miniaturization is achieved, but capacitive coupling effects become more problematic, affecting programming accuracy
Solution Approach 1:
The patent introduces the floating bit line as an intermediary element between the programming circuitry and the storage elements. This intermediary allows for indirect control of the programming process by enabling the bit line to float at a potential that compensates for capacitive coupling effects, thereby maintaining programming accuracy in scaled-down devices.
3Measurement precision
If the channel potential is fully inhibited to prevent capacitive coupling, then programming accuracy is improved, but programming speed is reduced
Solution Approach 1:
The patent applies partial action by allowing the channel potential to float rather than fully inhibiting it. This partial control approach enables the bit line to compensate for capacitive coupling effects without completely blocking the programming current, thereby maintaining both programming accuracy and acceptable programming speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces capacitive coupling effects, allowing for more accurate and efficient programming by controlling the channel potential, thereby maintaining the integrity of threshold voltage distributions and improving programming speed and accuracy.
Implementation Method 1
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The threshold voltage (Vth) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate.
Implementation Method 2
When programming an EEPROM or flash memory device, such as a NAND flash memory device in a NAND string, typically Vpgm is applied to the control gate and the bit line is grounded, causing electrons from the channel of a storage element to be injected into the floating gate.
Implementation Method 3
Vpgm is applied to the control gate and the bit line is grounded, causing electrons from the channel of a storage element to be injected into the floating gate
Data Source
Figure 1a~2
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AI summary
Partial speed (fine) and full speed (coarse) programming are achieved for a non-volatile memory system. During a program operation, in a first time period (tl-t3), bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed (fine programming) and bit lines of storage elements to be programmed at a full speed (coarse programming) are fixed at ground potential. In a second time period (t4-t5), the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain grounded. In a third time period (t5-t8), the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.