Floating Bitline ADC for Low-Power In-Memory Current Conversion
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Solution Overview
Problem
In memory arrays used for data storage and in-memory processing, efficiently measuring multiple analog currents generated by memory devices is challenging due to the need for high-power ADCs and sensitivity to device mismatches and process variations, making it inefficient to convert currents into digital signals effectively.
Innovation Solution
A system comprising a bitline connected to a column of memory cells, a digital-to-analog converter, and a voltage comparator that sums currents and compares the bitline voltage to a fixed voltage, allowing the digital-to-analog converter to generate current only until the bitline voltage reaches the fixed voltage, thereby determining the total current generated by selected memory cells without requiring high-gain amplifiers, reducing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple large, high-power ADCs are used to convert currents into voltage, then conversion capability is improved, but power consumption and chip area increase
Solution Approach 1:
The patent combines multiple current measurement functions into a single shared ADC. Multiple bitlines share a common ADC resource, allowing the system to convert multiple analog currents to digital signals using one converter instead of requiring separate ADCs for each current, thereby reducing overall power consumption and chip area while maintaining conversion capability.
Solution Approach 2:
The ADC is designed as a universal resource that can be multiplexed to convert currents from multiple different bitlines. The system enables one ADC to perform multiple conversion tasks sequentially or in parallel through time-multiplexing, making the converter multi-functional and eliminating the need for dedicated ADCs for each measurement channel.
2Measurement precision
If circuits are designed for measuring small analog currents in sub-micron technologies, then measurement capability is improved, but circuit size becomes bulky and sensitivity to mismatches increases
Solution Approach 1:
The patent introduces current mirror circuits as intermediary elements that transfer and replicate small analog currents from the memory bitlines to the ADC input. These current mirrors act as buffers that preserve the precision of small current measurements while isolating the sensitive measurement process from the ADC circuit, thereby reducing the direct complexity and sensitivity issues in the main measurement path.
3Device complexity
If dependency of bitline voltage to measured current is used for conversion, then simpler circuits with less power consumption are achieved, but conversion precision may be affected
Solution Approach 1:
The patent implements feedback mechanisms where the ADC conversion process incorporates voltage dependency compensation. The system measures the bitline voltage and uses this information to adjust or compensate for the voltage-dependent current characteristics during conversion, thereby maintaining high conversion accuracy despite using simpler voltage-dependent measurement circuits instead of complex constant-voltage measurement systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and precise conversion of analog currents to digital signals with low power consumption and reduced sensitivity to device mismatches and process variations, facilitating both data storage and in-memory computing applications.
Implementation Method 1
The bitline may be configured to sum up the current produced by the memory cells in the column
Implementation Method 2
The voltage comparator may be configured to measure a voltage on the bitline and compare it to a fixed voltage
Data Source
AI summary
Systems and methods with analog to digital converters are provided. The systems and methods may include a plurality of non-volatile memory cells that may be organized into an array. A bitline may be electrically coupled to a column of memory cells vertically arranged in the array. The bitline may be configured to sum up the current produced by the memory cells in the column. A digital-to-analog converter having an output electrically coupled to the bitline may be configured to generate a current and add it through the output to the bitline. A voltage comparator having an input that is electrically coupled to the bitline may be configured to measure a voltage on the bitline and compare it to a fixed voltage, and to stop the digital-to-analog converter from adding current to the bitline when the measured voltage exceeds the fixed voltage.