Floating Body Memory Cell Back Bias for Data Retention
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in maintaining memory cell states without interrupting access, particularly due to charge leakage in floating body DRAM cells and the need for periodic refresh operations, as well as the slower operation and limited endurance of non-volatile memory devices.
Innovation Solution
A method involving the application of a back bias to semiconductor memory cells to offset charge leakage, allowing for simultaneous access and maintenance of memory cell states without interrupting access, and the use of a floating body transistor design that combines volatile and non-volatile functionality for fast operation and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DRAM cells are used, then fast operation is achieved, but periodic refresh operations are required due to charge leakage
Solution Approach 1:
The patent applies preliminary action by performing a hold operation before the memory cell state degrades completely. A back bias is applied to the substrate terminal to prevent charge leakage from the floating body, thereby maintaining the memory cell state without requiring periodic refresh operations. This proactive approach preserves fast DRAM operation while extending data retention time.
2Duration of action of stationary object
If non-volatile memory devices are used, then data retention is improved, but operation speed decreases
Solution Approach 1:
The patent merges the advantages of both volatile and non-volatile memory by combining a floating body transistor structure with a substrate terminal capable of applying back bias. The floating body provides fast operation like volatile memory, while the substrate terminal with back bias capability enables extended data retention like non-volatile memory. This hybrid approach achieves both fast operation and improved data retention time.
3Area of stationary object
If floating body DRAM cells are used, then cell size is reduced, but charge leakage occurs requiring refresh operations
Solution Approach 1:
The substrate terminal acts as an intermediary element that mediates between the floating body and the bulk substrate. By applying a back bias through this intermediary terminal, the patent prevents charge leakage from the floating body without increasing the memory cell size. This intermediary mechanism maintains the compact cell structure while improving charge retention reliability.
4Duration of action of stationary object
If back bias is applied to offset charge leakage, then data retention is improved, but access to memory cells may be interrupted
Solution Approach 1:
The patent applies preliminary action by implementing the hold operation with back bias before memory access operations. By pre-applying the back bias to the substrate terminal, the memory cell state is stabilized in advance, allowing subsequent read and write operations to proceed without interruption. This proactive stabilization ensures both improved data retention and continuous memory access.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient maintenance of memory cell states without interrupting access and provides a universal memory device with fast operation and data retention capabilities, comparable to both volatile and non-volatile memory devices.
Implementation Method 1
DRAM based on the electrically floating body effect has been proposed... eliminates the capacitor used in the conventional 1T/1C memory cell
Implementation Method 2
applying a back bias to the cell to offset charge leakage out of a floating body of the cell
Data Source
AI summary
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.