Floating Body Memory Cell with Charge Trap Layer for Multi-bit Storage

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Solution Overview

Problem

Current memory devices face limitations in integration density and capacity due to the need for multiple memory cells to store data, with flash memory being unsuitable for frequent data rewriting and DRAM requiring periodic refreshment to maintain data.

Innovation Solution

A semiconductor memory device with a floating body, gate electrode, source and drain regions, and a charge trap layer that allows for writing and reading of multiple bits of data using charge trapping and hole storage methods, enabling multi-bit data storage in a single cell.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If flash memory is used to maintain data when power is turned off, then data retention capability is improved, but the number of times writing and erasing data can be repeated is limited

Engineering Contradiction:

Improvedata retention capabilityVSAvoidwriting and erasing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The memory cell is segmented into two distinct storage regions: a charge trap layer for non-volatile data retention and a floating body for volatile data storage. This segmentation allows the system to leverage the advantages of both flash memory (data retention) and DRAM (fast writing) by storing different types of data in different regions, thereby resolving the contradiction between data retention capability and writing speed.

Inventive Principle:

Principle #1Segmentation

2Loss of time

If DRAM is used to allow frequent rewriting of data, then the number of times writing data can be repeated is improved, but data cannot be maintained when power is turned off

Engineering Contradiction:

Improvewriting timeVSAvoiddata retention capability

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

3Quantity of substance

If multiple memory cells are used to increase storage capacity, then memory capacity is improved, but integration density is reduced

Engineering Contradiction:

Improvememory capacityVSAvoidintegration density

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The invention merges two storage functions (non-volatile charge trapping and volatile floating body storage) into a single memory cell structure. By combining the charge trap layer and floating body in one cell, the system achieves multi-bit storage capacity without increasing the number of physical cells, thereby improving integration density while maintaining high memory capacity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The single memory cell structure is designed to perform multiple functions: storing non-volatile data in the charge trap layer, storing volatile data in the floating body, and enabling multi-bit storage capacity. This multi-functionality allows one cell to replace what would traditionally require multiple cells, improving integration density.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances integration density and capacity by allowing two or more bits to be stored in one cell, improving the memory device's performance and reducing the need for multiple cells, thus addressing the limitations of existing technologies.

Implementation Method 1

Trapping the charge in the charge trap layer may include using hot carrier injection (HCI) or Fowler-Nordheim (FN) tunneling

Methodology Applied

Scientific EffectHot carrier injection:

Implementation Method 2

Trapping the charge in the charge trap layer may include using hot carrier injection (HCI) or Fowler-Nordheim (FN) tunneling

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Implementation Method 3

An impact ionization method, a gate-induced drain leakage (GIDL) method and/or a bipolar junction transistor (BJT) method may be used for storing holes in the floating body

Methodology Applied

Scientific EffectImpact ionization:

Implementation Method 4

An impact ionization method, a gate-induced drain leakage (GIDL) method and/or a bipolar junction transistor (BJT) method may be used for storing holes in the floating body

Methodology Applied

Scientific EffectGate-induced drain leakage:

Data Source

PatentUS8169823B2Memory devices having volatile and non-volatile memory characteristics and methods of operating the same

Publication Date: 2012.05.01 SAMSUNG ELECTRONICS CO LTD

AI summary

Multi-bit semiconductor memory devices having both volatile and nonvolatile memory characteristics and methods of operating the same are disclosed, the semiconductor memory device including a floating body on an upper region of a substrate, a gate electrode on the floating body and electrically insulated from the floating body, source and drain regions on the substrate adjacent to the gate electrode and a charge trap layer between the floating body and the gate electrode, where first bit data is written in one of the charge trap layer and the floating body, and second bit data is written in one of the charge trap layer and the floating body in which first bit data is not written.