Floating Body Contact Circuit for MOSFET ESD and Switching Speed
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Solution Overview
Problem
Semiconductor devices, particularly MOSFETs on SOI and SOS substrates, face challenges in improving ESD performance and switching speed due to accumulated charge, which introduces harmonic distortion, intermodulation distortion, and reduces breakdown voltage, while larger gate resistors enhance ESD handling but increase switching time and insertion loss.
Innovation Solution
Incorporating an accumulated charge sink (ACS) and a switchable gate resistor module (SGRM) to manage accumulated charge and optimize gate resistance, allowing for improved ESD handling and switching speed by dynamically adjusting resistance based on operational requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger gate resistors are used to enhance ESD handling, then ESD performance is improved, but switching time increases and insertion loss increases
Solution Approach 1:
The patent applies dynamics by making the gate resistance variable rather than fixed. A switchable gate resistor module is implemented that can dynamically adjust the gate resistance value based on operational conditions. During ESD events, higher resistance is applied to improve ESD handling, while during normal switching operations, lower resistance is used to maintain fast switching speed and low insertion loss.
Solution Approach 2:
The patent changes the resistance parameter of the gate resistor from a fixed value to a variable value that can be adjusted based on operational requirements. An accumulated charge sink is also employed to actively manage charge accumulation in the body, allowing the device to maintain optimal performance across different operating conditions by adjusting electrical parameters in real-time.
2Productivity
If accumulated charge is present in floating body devices, then device operation is enabled, but harmonic distortion increases, intermodulation distortion increases, and breakdown voltage decreases
Solution Approach 1:
The patent extracts the harmful accumulated charge from the floating body through an accumulated charge sink. This sink provides a dedicated path for charge to be removed from the body, separating the charge accumulation function from the normal device operation. By extracting the harmful charge carriers, the device maintains good linearity and breakdown voltage while still enabling proper operation.
Solution Approach 2:
The accumulated charge sink acts as an intermediary element between the floating body and the charge carriers. It mediates the charge management by providing a controlled path for charge removal, allowing the device to operate with minimal accumulated charge and thus reducing harmonic and intermodulation distortion while maintaining breakdown voltage.
Data Source
AI summary
Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.


