Floating Body Sidewall Doping for Leakage Reduction
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Solution Overview
Problem
In semiconductor memory apparatus, the reduction in size of unit cells leads to increased leakage currents and punch-through phenomena, affecting the reliability and integration of floating body transistors, especially due to challenges in forming effective local halo regions as design rules shrink.
Innovation Solution
A method is introduced where a local doped region is expanded and etched to cover the sidewalls of floating bodies, using a zero-degree ion tilt implantation and thermal processes to prevent punch-through, and forming a wider lower region of the local doped area to enhance isolation and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of unit cells is reduced to increase integration density, then the degree of integration is improved, but leakage currents increase and punch-through phenomena occur
Solution Approach 1:
The patent applies local quality by forming a local doped region specifically at the lower portion of the floating body where punch-through occurs, rather than uniformly doping the entire structure. This localized doping approach targets the specific problem area (the region prone to punch-through) while maintaining the overall floating body structure needed for high integration density
Solution Approach 2:
The patent implements preliminary action by forming the local doped region before finalizing the floating body structure. This preliminary doping prevents punch-through phenomena from occurring in the first place, allowing the unit cell to maintain high integration density without suffering from leakage issues that would otherwise require larger spacing between components
2Reliability
If a local halo region is formed to prevent punch-through, then reliability is improved, but manufacturing complexity increases due to difficulty in forming effective halo regions at reduced design rules
Solution Approach 1:
The patent inverts the conventional approach by forming the local doped region using a reverse-tilt ion implantation method. Instead of using standard tilt angles that are difficult to control at reduced design rules, the patent uses a reverse tilt direction that simplifies the manufacturing process while effectively preventing punch-through phenomena
Solution Approach 2:
The patent applies parameter changes by modifying the ion implantation tilt angle to zero degrees for the local doped region formation. This parameter change simplifies the manufacturing process by eliminating the need for precise tilt angle control, while still achieving effective punch-through prevention through the localized doping
3Quantity of substance
If the floating body volume is increased to store more charges, then data storage capability is improved, but leakage currents increase due to larger junction areas
Solution Approach 1:
The patent applies local quality by selectively doping only the lower portion of the floating body where punch-through occurs, rather than uniformly doping the entire floating body structure. This allows the upper portion to maintain large volume for charge storage while the lower portion has controlled doping to prevent leakage
Solution Approach 2:
The patent segments the floating body into different functional regions: the upper portion maintains large volume for charge storage, while the lower portion has localized doping for leakage prevention. This segmentation allows simultaneous optimization of both charge storage capacity and leakage reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents punch-through phenomena, improving the integration and stability of semiconductor devices by increasing the volume of the floating body and reducing leakage currents, thus enhancing the reliability of semiconductor memory apparatus.
Implementation Method 1
expanding a local doped region formed between gate patterns by a thermal process to form an expanded local doped region
Implementation Method 2
performing an ion implantation process on the silicon-on-insulator substrate exposed between the gate patterns to form the local doped region
Data Source
AI summary
A method for fabricating a semiconductor device comprises: performing a thermal process to expanding a local doped region formed between gate patterns on a semiconductor substrate; and etching a central region of an expanded local doped region so that the expanded local doped region remains at the total area of sidewalls of floating bodies isolated from each other.