Floating Body DRAM Conditional Writeback Logic
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Solution Overview
Problem
Floating body DRAMs face signal attenuation during read operations, leading to power dissipation issues, which are not effectively addressed by existing technologies.
Innovation Solution
Implementing conditional writeback logic in memory devices that selectively performs writeback operations based on a random or adaptive probability, reducing power dissipation while maintaining the benefits of writeback operations to address sense voltage attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If writeback operations are performed for every read operation, then sense voltage attenuation is addressed, but power dissipation increases
Solution Approach 1:
The patent implements dynamic conditional writeback logic that adapts the writeback operation frequency based on detected signal attenuation patterns. The system transitions from static always-writeback to dynamic selective-writeback, adjusting operations in real-time based on actual signal conditions rather than following a fixed pattern for every read operation.
Solution Approach 2:
The patent applies partial action by performing writeback operations only when necessary rather than for every read operation. The conditional writeback logic determines the minimal required writeback frequency to maintain signal integrity, avoiding excessive writeback operations that would waste power while ensuring sufficient writeback to prevent signal attenuation.
2Use of energy by moving object
If writeback operations are reduced to minimize power dissipation, then power consumption decreases, but signal attenuation may worsen
Solution Approach 1:
The patent incorporates feedback mechanisms where the conditional writeback logic monitors signal attenuation patterns and adjusts writeback operation frequency accordingly. The system uses feedback from detected signal conditions to dynamically control when writeback operations should occur, ensuring signal integrity is maintained while optimizing power consumption based on actual operational needs.
Data Source
AI summary
Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.