Floating-Body Memory Cell Gate Segmentation for Coupling Noise
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Solution Overview
Problem
Capacitive coupling between the word line and the floating body in capacitor-less single-transistor DRAMs leads to noise transmission and erroneous reading or rewriting, making it difficult to achieve high-density and high-performance memory cells.
Innovation Solution
The semiconductor-element-including memory device features a specific structure with multiple semiconductor bodies, impurity regions, and gate conductor layers arranged to minimize capacitive coupling, allowing for controlled voltage application to retain or discharge electrons and holes, thereby reducing noise and improving data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor-less single-transistor DRAM structure is used to achieve high density, then device integration density is improved, but capacitive coupling noise between word line and floating body increases causing erroneous reading and rewriting
Solution Approach 1:
The gate conductor layer is divided into multiple segments (first gate conductor layer and second gate conductor layer) that can be controlled independently. This segmentation allows differential voltage application to reduce capacitive coupling noise while maintaining high-density integration of the memory cell structure.
Solution Approach 2:
The invention changes the voltage parameters applied to different gate conductor layers during read and write operations. By applying specific voltage combinations (e.g., V1 and V2 with V1>V2 for read operation), the noise from capacitive coupling is minimized while maintaining reliable data storage and retrieval in the high-density capacitor-less structure.
2Device complexity
If floating body structure is used to eliminate capacitor, then device complexity is reduced, but noise from capacitive coupling affects reading and writing reliability
Solution Approach 1:
The gate conductor layer is segmented into multiple independently controllable layers. This segmentation maintains the simplicity of the capacitor-less floating body structure while enabling noise reduction through differential voltage control, thus preserving reading and writing reliability without increasing structural complexity.
Solution Approach 2:
Multiple gate conductor layers act as intermediaries between the control signals and the floating body. By controlling the voltage differences between these intermediary layers, capacitive coupling noise is reduced while the floating body structure remains simple and capacitor-less, maintaining both low complexity and high reliability.
3Object-affected harmful factors
If synchronous or asynchronous driving of gate conductor layers is implemented, then noise interference is minimized, but control complexity increases
Solution Approach 1:
The gate conductor layer is segmented into multiple layers that can be driven synchronously or asynchronously. This segmentation provides flexible control options: synchronous driving for simple operations and asynchronous driving for noise-sensitive operations, allowing noise interference to be minimized without requiring complex control mechanisms for all operations.
Solution Approach 2:
The control mechanism is made dynamic by allowing both synchronous and asynchronous driving modes for the gate conductor layers. This dynamic control approach enables the system to adapt to different operational requirements, minimizing noise interference when needed while maintaining simpler control for routine operations, thus balancing noise reduction with control complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the operational margin between '1' and '0' states, enabling high-density and high-performance dynamic flash memory cells with reduced erroneous readings and writings.
Implementation Method 1
the gate-induced drain leakage current, electron-positive hole pairs are generated by impact ionization
Data Source
AI summary
Si bodies 24aa to 24ad, 24ba to 24bd, and 45a to 45d are disposed parallel to a substrate 20 and are adjacent to each other in a horizontal direction at regular intervals. A HfO2 layer 27b surrounds the Si bodies 24aa to 45d. TiN layers 34a to 34d surround the HfO2 layer 27b, are isolated from each other, and are each formed of portions contiguous in the horizontal direction. The Si bodies 45a to 45d are formed stepwise in cross-sectional view in the terminating end in the horizontal direction. Metal wiring layers 52a to 52d are connected to the TiN layers 34a to 34d and extend up to above an insulating layer 50 through contact holes 51a to 51d extending in a vertical direction from the terminating ends of the TiN layers 34a to 34d. The metal wiring layers 52a to 52d are connected to word lines WL1 to WL4.