Floating Body Memory Array With Programmable Word Length
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Solution Overview
Problem
Conventional memory cell technologies face challenges in efficiently programming and reading data with low power consumption while maintaining data retention and minimizing disturbance to unselected memory cells in dynamic random access memory (DRAM) arrays.
Innovation Solution
The implementation of an integrated circuit device with a memory cell array using electrically floating body transistors, where write and read operations are controlled through specific signal circuits that apply temporal and constant voltage signals to prevent charge loss and data disturbance in unselected cells, allowing for variable word length programming and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional memory cell programming and reading operations are performed, then data can be stored and retrieved, but power consumption increases and unselected memory cells may be disturbed
Solution Approach 1:
The memory array is divided into multiple independently controllable banks, where only the selected bank undergoes programming or reading operations. Each bank has its own word lines and bit lines, allowing operations to be localized and preventing disturbance to unselected cells in other banks.
Solution Approach 2:
Different voltage levels and control signals are applied to different regions of the memory array based on selection status. Selected cells receive full programming/read voltages, while unselected cells receive reduced or zero voltages to prevent charge injection and maintain data retention.
2Adaptability or versatility
If fixed word length memory architecture is used, then circuit design is simplified, but flexibility in data access and processing is reduced
Solution Approach 1:
The memory system implements dynamic word length configuration through programmable control logic that can adjust the number of active bit lines and corresponding data buses based on the required data width. This allows the same physical memory array to support different word lengths (e.g., 8-bit, 16-bit, 32-bit) without hardware changes.
Solution Approach 2:
The memory controller is designed with universal interfaces and control logic that can accommodate multiple word length configurations. The same basic memory cell structure and access mechanism serve both fixed and variable word length modes, eliminating the need for separate dedicated circuits for each configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient data programming and reading with reduced power consumption, maintaining data integrity and allowing for flexible word length configurations, thereby enhancing data retention and operational speed.
Implementation Method 1
the memory cell includes a transistor having an electrically floating body in which an electrical charge is stored
Implementation Method 2
accumulating majority carriers (in this example, 'holes') 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22
Implementation Method 3
Emitting or ejecting majority carriers 34 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction
Data Source
AI summary
A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed.