Floating-Body Memory Cell Layout for Disturb-Resistant Arrays
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Solution Overview
Problem
There is a need to improve the disturb resistance in semiconductor memory cells, particularly in memory arrays where operations on one cell can inadvertently affect surrounding cells, and existing technologies have limitations in scaling and efficiency.
Innovation Solution
A semiconductor memory cell design incorporating an electrically floating body transistor and an access transistor, with specific configurations such as different capacitances and gate lengths, and the use of a dummy gate region, to enhance bi-stability and reduce disturb effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM cell designs are used, then data storage is achieved, but disturb resistance is poor and scaling is limited
Solution Approach 1:
The patent applies parameter changes by modifying the transistor body region to be electrically floating (changing the electrical state parameter), and by adjusting capacitance values and gate lengths to optimize bi-stability. This resolves the contradiction by improving disturb resistance through parameter optimization without fundamentally changing the cell structure complexity.
Solution Approach 2:
The patent segments the memory cell into distinct functional regions with different capacitances and gate lengths, allowing independent optimization of each region's properties to enhance overall disturb resistance while maintaining manageable device complexity.
2Ease of operation
If memory operations are performed on one cell, then data access is enabled, but surrounding cells are inadvertently affected
Solution Approach 1:
The patent applies local quality by giving different capacitance values and gate lengths to specific regions within the memory cell, creating localized electrical characteristics that confine the effects of operations to the targeted cell. This resolves the contradiction by reducing cell interference through localized property differentiation while maintaining ease of operation.
3Productivity
If existing memory technologies are used, then data storage is achieved, but scaling to smaller feature sizes is limited
Solution Approach 1:
The patent enables scaling by changing key parameters such as making the body region electrically floating and optimizing capacitance and gate length ratios, allowing the cell to maintain improved disturb resistance at smaller feature sizes. This resolves the contradiction by achieving both scaling efficiency and maintained reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves the bi-stability and disturb resistance of semiconductor memory cells, allowing for more efficient operation and reduced interference between memory cells, thereby enhancing the performance and reliability of memory arrays.
Implementation Method 1
a first transistor (40) having a floating body transistor
Data Source
AI summary
A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.