Floating Body Memory Cell Charge Storage Design
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Solution Overview
Problem
Conventional floating body memory cells suffer from poor data retention and signal fluctuation due to charge leakage and recombination, especially during write and read operations, and have limited scalability due to the size of the capacitor.
Innovation Solution
A memory cell design featuring a floating body with a bias gate and dielectric layer surrounding a charge storing region, which is remote from the source and drain regions, and a passage coupling the first and second regions to enhance charge retention and minimize disturbance, using epitaxial silicon and high-K dielectric materials to increase capacitance and reduce charge recombination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charges are stored in a floating body adjacent to source and drain regions, then write and read operations can be performed, but charge leakage and recombination occur causing poor data retention and signal fluctuation
Solution Approach 1:
The patent extracts the charge storage function from the traditional floating body location (adjacent to source/drain) and relocates it to a remote second region. This separation removes the harmful interaction between stored charges and the source/drain regions, eliminating charge leakage and recombination while preserving data retention capability
Solution Approach 2:
The patent introduces a passage structure as an intermediary element that couples the first region (between source and drain) and the second region (remote storage location) through an insulation layer. This intermediary enables charge transfer during operations while maintaining spatial separation to prevent charge loss
2Quantity of substance
If a conventional capacitor is used in memory cell, then charge can be stored, but the size limits scalability
Solution Approach 1:
The patent merges the charge storage function directly into the transistor structure by utilizing the floating body as the storage element, eliminating the need for a separate capacitor component. This integration reduces device complexity and enables better scalability while maintaining charge storage capacity
Solution Approach 2:
The floating body structure serves multiple functions: it acts as both the transistor body and the charge storage element. This multi-functionality eliminates the need for additional capacitor components, reducing overall device size and improving scalability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves data retention and minimizes signal fluctuation by storing charges remotely from the source and drain regions, allowing for more charge storage and reduced charge loss, while being scalable and adaptable for smaller feature sizes.
Implementation Method 1
A memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. The plurality of dielectric layers may include a first dielectric layer formed adjacent a vertical surface of the second region and between the vertical surface of the second region and the bias gate
Implementation Method 2
a passage extending through the insulation layer and coupling the first region to the second region
Data Source
AI summary
An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.