Floating-Body Memory Cell Structure for Disturb-Resistant Bi-Stability
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Solution Overview
Problem
There is a need to improve the disturb resistance in semiconductor memory cells, particularly in memory arrays where operations on one cell can inadvertently affect surrounding cells, and existing technologies have limitations in scaling and efficiency.
Innovation Solution
A semiconductor memory cell design incorporating an electrically floating body transistor and an access transistor, with specific configurations of insulating layers, gate regions, and capacitance differences to enhance bi-stability and reduce disturb effects, allowing for improved operational states and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM cell designs are used, then data storage is achieved, but disturb resistance is poor and scaling is limited
Solution Approach 1:
The patent changes the electrical state of the body region from grounded to floating, and adjusts the insulating layer thickness parameters (first thickness different from second thickness) to create asymmetric charge storage conditions. This enables bi-stable operation with improved disturb resistance while maintaining a scaled-down cell structure without conventional capacitors
Solution Approach 2:
The patent introduces vertical dimensionality through the asymmetric insulating layer configuration (different thicknesses in different directions) and utilizes the body effect in the vertical direction to create stable charge storage states, enabling improved disturb resistance in a three-dimensional transistor structure
2Area of stationary object
If capacitor-based memory cells are used, then data storage is achieved, but cell size is large and scaling is difficult
Solution Approach 1:
The patent extracts and eliminates the external capacitor component from the memory cell structure, using only the transistor's floating body region for charge storage. This reduces the memory cell area significantly while maintaining data retention reliability through the bi-stable floating body mechanism
Solution Approach 2:
The patent merges the storage function previously separated in dedicated capacitors into the transistor's body region itself. The floating body of the access transistor serves dual purposes as both the access mechanism and the storage element, reducing overall cell size while maintaining reliability
3Stability of the object's composition
If symmetric insulating layers are used, then manufacturing is simplified, but bi-stability is reduced
Solution Approach 1:
The patent deliberately introduces asymmetry in the insulating layer thickness (first thickness different from second thickness) to create unequal potential barriers in different directions. This asymmetric configuration is essential for establishing bi-stable operation, where the floating body can maintain either high or low potential states with appropriate stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances bi-stability and reduces disturb resistance in semiconductor memory cells, enabling more efficient and reliable data storage by optimizing the configuration of floating body regions and access devices, leading to improved scalability and operational stability.
Implementation Method 1
a back-bias region configured to generate impact ionization when the semiconductor memory cell is in one of first and second states
Implementation Method 2
A memory transistor is provided including a bi-stable floating body transistor having a first floating body region
Data Source
AI summary
A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.