Floating Body Memory Cell Contact Reduction
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Solution Overview
Problem
There is a need for semiconductor memory devices that are smaller in size than currently existing devices, as conventional DRAM cells face challenges in scaling due to the necessity of maintaining capacitance value and require periodic refresh operations.
Innovation Solution
The development of a semiconductor memory device with an electrically floating body transistor, where memory cells are connected in series or parallel to reduce the number of contacts, allowing for a compact memory array with fewer contacts and enabling smaller cell sizes by eliminating the need for a capacitor in the 1T/1C memory cell structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional 1T/1C memory cell structure is used, then data storage function is achieved, but cell size is large and scaling is difficult
Solution Approach 1:
The patent extracts and eliminates the capacitor component from the conventional 1T/1C memory cell structure, retaining only the transistor element. This extraction enables the memory cell to function without the capacitor, thereby reducing cell size and simplifying the overall structure while maintaining data storage capability through the floating body effect.
Solution Approach 2:
The patent changes the operational parameters of the transistor by utilizing the floating body effect, where the body region is electrically isolated and accumulates charge. This parameter change allows the transistor to replace the traditional capacitor-function, enabling data storage without requiring a separate capacitor component and thus reducing cell size.
2Ease of manufacture
If number of contacts is reduced, then manufacturing complexity is decreased, but electrical connection reliability may be affected
Solution Approach 1:
The patent merges the functions of multiple contacts into fewer contacts by utilizing the floating body structure. The reduced number of contacts are designed to establish multiple electrical connections simultaneously, thereby simplifying the fabrication process while maintaining reliable electrical connections through the merged contact architecture.
3Volume of moving object
If capacitor is eliminated from 1T/1C structure, then cell size is reduced, but data retention capability must be maintained
Solution Approach 1:
The patent implements self-service by utilizing the floating body region of the transistor itself to perform the data storage function traditionally performed by the capacitor. The floating body accumulates and retains charge internally within the transistor structure, enabling the device to serve its own data retention needs without requiring an external capacitor component.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for a more compact memory array with reduced contact requirements, enabling smaller cell sizes and improved scalability, while maintaining data storage efficiency without the need for periodic refresh operations.
Implementation Method 1
DRAM based on the electrically floating body effect has been proposed
Data Source
AI summary
An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.