Floating Body Memory Standby Power Reduction via Data Inversion
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAM cells without capacitors, face challenges in reducing standby power consumption due to the presence of bi-stable states that lead to active leakage currents, which increase power usage.
Innovation Solution
Implementing a method to count the number of bits in each state within a floating body memory array, setting an inversion bit when necessary, and inverting data before writing to reduce standby power by optimizing the state of memory cells and using a vertical bipolar holding mechanism efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If floating body memory cells are used to eliminate capacitors and reduce cell size, then manufacturing ease and cell density improve, but standby power consumption increases due to active leakage currents from bi-stable states
Solution Approach 1:
The patent applies local quality by differentiating between memory cells that need to maintain bi-stable states (for data storage) and those that can be in low-power states. By selectively controlling which cells remain in high-power bi-stable mode versus which cells transition to low-power single-state mode, the system reduces overall standby power while preserving data storage functionality where needed.
Solution Approach 2:
The patent segments the memory array into different operational regions or groups of cells. Some segments maintain the full bi-stable floating body functionality for active data storage, while other segments are transitioned to reduced-power states. This segmentation allows the system to optimize power consumption based on actual data retention requirements across different portions of the memory array.
2Reliability
If bi-stable states are maintained in all memory cells for data storage, then data retention capability improves, but standby power consumption increases due to active leakage currents
Solution Approach 1:
The patent implements partial action by maintaining bi-stable states in only the necessary portion of memory cells rather than all cells. By assessing which cells actually require data retention and keeping those in bi-stable mode while allowing others to enter low-power states, the system achieves sufficient data retention capability with reduced power consumption.
Solution Approach 2:
The patent changes the operational parameters of memory cells dynamically. Cells can transition between bi-stable mode (higher power, full data retention) and reduced-power mode (lower power, selective data retention). This parameter change allows the system to adapt power consumption levels based on actual data storage requirements, resolving the contradiction between reliability and energy use.
3Stability of the object's composition
If vertical bipolar holding mechanism is activated to maintain memory cell states, then data stability improves, but power consumption increases due to active leakage currents
Solution Approach 1:
The patent implements periodic action through refresh operations. Instead of continuously maintaining all cells in high-power bi-stable states, the system periodically refreshes data in cells that transition to low-power states. This periodic refresh approach maintains data stability for essential information while allowing non-critical cells to enter energy-saving modes, reducing overall power loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces standby power consumption by ensuring that only necessary memory cells are in the high power state, thereby minimizing active leakage currents and overall power usage.
Implementation Method 1
DRAM based on the electrically floating body effect has been proposed both in silicon-on-insulator (SOI) substrate
Implementation Method 2
the applied back bias which causes impact ionization and generates holes to compensate for the charge leakage current
Data Source
AI summary
Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.