Floating Body Memory Cell Layout for High-Density DRAM Scaling
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing cell size and increasing storage density while maintaining effective read and write operations, particularly in scaling down the 1T/1C DRAM cells and efficiently utilizing floating body transistors.
Innovation Solution
The development of a semiconductor memory device with an electrically floating body that utilizes a back bias region to reduce device size, allowing for the storage of one or more bits in a single memory cell, and employs a half-transistor structure with a vertical arrangement of diffusion regions beneath the surface, eliminating the need for surface contacts and reducing the number of required contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 1T/1C DRAM cells are scaled down, then storage density is improved, but manufacturing difficulty and capacitance maintenance become problematic
Solution Approach 1:
The patent removes the capacitor component from the conventional 1T/1C DRAM cell structure, extracting only the transistor element. This eliminates the need to maintain capacitance values while preserving memory functionality through the floating body effect, directly resolving the manufacturing difficulty associated with capacitance maintenance at scaled dimensions.
Solution Approach 2:
The patent changes the operational parameters of the transistor by utilizing the floating body effect, where charge accumulation in the body region modifies the transistor's threshold voltage and conductance. This parameter change enables memory storage without requiring a capacitor, allowing continued scaling while maintaining manufacturability.
2Area of stationary object
If floating body transistors are used to eliminate capacitors, then cell size is reduced, but contact requirements increase
Solution Approach 1:
The patent merges the source and drain contacts into a single shared contact structure at the surface, while the floating body region serves dual purposes as both the transistor body and the charge storage region. This merging reduces the number of required contacts and simplifies the overall device structure despite the unconventional floating body configuration.
Solution Approach 2:
The patent moves the charge storage function from the surface plane to the vertical dimension by creating a floating body region beneath the surface. This dimensional transition allows the floating body to be accessed and controlled through vertical field effects rather than requiring additional surface contacts, thereby reducing contact complexity.
3Area of stationary object
If back bias regions are introduced to reduce device size, then area is reduced, but device complexity increases
Solution Approach 1:
The back bias region is designed to serve multiple functions simultaneously: it provides electrical contact to the floating body for charge control, acts as a doping region to establish the floating body potential, and serves as part of the transistor structure itself. This multi-functionality reduces the need for separate components, thereby limiting the increase in device complexity despite the added functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a smaller memory cell size, improved storage density, and efficient read and write operations, with the ability to maintain memory states through a holding operation that balances charge leakage and replenishment, enhancing the memory window and enabling multi-bit operations without increasing area.
Implementation Method 1
a holding operation that balances charge leakage and replenishment
Implementation Method 2
semiconductor memory device with an electrically floating body that utilizes a back bias region
Data Source
AI summary
An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to the buried region.