Floating Body Memory Cell String Reduces Contact Count
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for semiconductor memory devices that are smaller in size than currently existing devices, as conventional DRAM cells face challenges in scaling due to capacitance value maintenance and require periodic refresh operations.
Innovation Solution
The development of a semiconductor memory device with an electrically floating body transistor, where memory cells are connected in series or parallel to reduce the number of contacts, allowing for a compact memory array with fewer contacts and enabling efficient data storage in a smaller form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional DRAM cells are scaled down to reduce size, then device dimensions are reduced, but capacitance value maintenance becomes difficult and periodic refresh operations are required
Solution Approach 1:
The patent extracts the capacitor component from the conventional 1T/1C memory cell structure, eliminating the need for periodic refresh operations. The floating body transistor structure replaces the capacitor-based charge storage mechanism with a transistor-based storage mechanism that does not require refresh cycles, thereby solving the reliability issue while maintaining small device dimensions.
Solution Approach 2:
The patent changes the fundamental storage mechanism parameter from capacitor-based charge storage to floating body transistor-based storage. This parameter change enables the memory cell to maintain data without periodic refresh operations, addressing the reliability concern while keeping the device size small.
2Length of moving object
If conventional DRAM cells are scaled down, then feature size is reduced, but the number of contacts required increases complexity
Solution Approach 1:
The patent merges multiple memory cells into a shared string structure where a single contact can access multiple cells through the floating body transistor mechanism. This merging approach reduces the total number of contacts required compared to conventional scaled-down DRAM cells, thereby reducing device complexity while maintaining small feature sizes.
Solution Approach 2:
The floating body transistor structure provides multi-functionality by serving as both the storage element and the access mechanism for multiple memory cells within a string. This universal structure eliminates the need for separate contacts for each cell, reducing overall contact complexity while enabling continued scaling to smaller feature sizes.
3Speed
If more contacts are used to access memory cells, then data access speed is improved, but device area increases
Solution Approach 1:
The patent transitions from a two-dimensional array structure requiring multiple contacts to a three-dimensional string structure where cells are stacked vertically. This dimensional change allows multiple memory cells to be accessed through a single contact point, maintaining data access speed while significantly reducing the device footprint area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for a compact memory array with reduced contact numbers, enabling efficient data storage and scaling while eliminating the need for periodic refresh operations, thus addressing the size and scalability challenges of conventional DRAM cells.
Implementation Method 1
DRAM based on the electrically floating body effect has been proposed
Data Source
AI summary
An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.