Asymmetric Floating Body Memory Transistors for Charge Retention
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Solution Overview
Problem
Floating body memory technologies face challenges in achieving long-term data retention, sensitivity to temperature variations, and slow read/write speeds, which are exacerbated by scaling to smaller device sizes, leading to reliability issues and charge leakage.
Innovation Solution
Implementing asymmetric transistors with varying semiconductor material thickness, doping concentration, and bandgap differences in thin-film transistors (TFTs) for floating body memory cells, allowing for improved charge confinement and reliability, and enabling stacked architectures compatible with advanced CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If floating body memory is scaled to smaller device sizes, then device density is improved, but charge leakage and reliability issues worsen
Solution Approach 1:
The patent applies local quality by introducing asymmetric semiconductor materials with different properties at different locations within the transistor structure. Specifically, the first semiconductor material is placed between the first S/D contact and the first S/D region, while the second semiconductor material is placed between the second S/D contact and the second S/D region. This spatial differentiation allows optimization of charge confinement in specific regions to prevent leakage while maintaining high device density.
Solution Approach 2:
The patent implements asymmetry by using different semiconductor materials on the write side and read side of the transistor. The first semiconductor material and second semiconductor material differ in at least one of thickness, bandgap, or doping concentration. This asymmetric configuration enables differential charge confinement characteristics that address reliability issues while allowing continued scaling for high density.
2Reliability
If asymmetric transistor structures are implemented, then charge confinement and reliability are improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by varying key semiconductor material parameters (thickness, bandgap, doping concentration) to optimize charge confinement. The first semiconductor material may have different thickness, bandgap energy, or doping levels compared to the second semiconductor material. These parameter variations are implemented within the existing transistor fabrication framework, improving reliability without requiring fundamental structural redesign.
Solution Approach 2:
The patent uses composite materials by combining different semiconductor materials in the transistor structure. The first semiconductor material and second semiconductor material are distinct materials with different electrical and physical properties. This composite approach enables tailored charge confinement characteristics in different regions of the device, achieving superior reliability while maintaining compatibility with standard semiconductor manufacturing processes.
Data Source
AI summary
Transistor designs for floating body memory, and associated devices and systems, are disclosed. In one aspect, a transistor of a floating body memory cell includes a layer of a first semiconductor material between a first S/D contact and a first S/D region of the transistor, and a layer of a second semiconductor material between a second S/D contact and a second S/D region of the transistor, where the first and second semiconductor materials differ in at least one of a thickness, a bandgap, or a doping concentration.