Multi-bit Memory Cell Using Floating Body Transistor
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Solution Overview
Problem
Conventional dynamic random access memory (DRAM) cells with electrically floating bodies face limitations in storing multiple bits per cell, as they typically only have two distinct current states corresponding to two logical states, limiting data storage capacity and efficiency.
Innovation Solution
The implementation of an integrated circuit device with a memory cell featuring an electrically floating body transistor that can store more than two data states by using intrinsic bipolar transistor currents and specific control signals to manage charge in the body region, allowing for the generation of multiple bipolar transistor currents to represent different data states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM cells with electrically floating bodies are used, then the device structure is simple and easy to manufacture, but the data storage capacity is limited to two bits per cell
Solution Approach 1:
The patent applies parameter changes by utilizing different current states of the bipolar transistor to represent multiple data states. Specifically, it uses at least four distinct current states (Ioff, I1, I2, I3) to encode two bits of data, transforming the conventional two-state system into a multi-state system through controlled charge accumulation in the floating body region.
Solution Approach 2:
The patent implements multi-functionality by enabling the single memory cell to store multiple bits of data through the intrinsic bipolar transistor effect. The same floating body structure that traditionally provided only two states now provides multiple current states, allowing one cell to perform the function of multiple cells while maintaining the basic one-transistor architecture.
2Quantity of substance
If multiple data states are stored in the floating body region, then data storage capacity increases, but the difficulty of detecting and measuring data states increases
Solution Approach 1:
The patent employs feedback mechanisms through sense amplifiers that detect the bipolar transistor current states and provide feedback signals to determine the stored data. The sense amplifier compares the actual current state with reference levels to accurately identify which of the multiple data states is present, enabling reliable detection despite the increased complexity of measuring multiple current levels.
Solution Approach 2:
The patent introduces intermediary elements including sense amplifiers and reference current sources that mediate between the floating body charge states and the external readout circuitry. These intermediaries convert the internal charge states into measurable current signals and provide the necessary signal conditioning to distinguish between multiple data states accurately.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the storage of multiple bits per cell, enhancing data storage capacity and efficiency by clearly distinguishing between various data states through controlled bipolar transistor currents, thereby improving read and write operations.
Implementation Method 1
the electrically floating body effect of SOI transistors. In this regard, the dynamic random access memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation layer (or non-conductive region, for example, in a bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body region of the SOI transistor.
Implementation Method 2
Accumulating majority carriers (in this example, 'holes') 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22, is representative of a logic high or '1' data state.
Implementation Method 3
Emitting or ejecting majority carriers 34 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low or '0' data state.
Data Source
AI summary
There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc.) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory).