Floating-Body NAND String for Capacitor-Free Memory Isolation
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Solution Overview
Problem
Conventional semiconductor memory devices, particularly DRAM cells, face challenges in scaling to smaller feature sizes and maintaining data integrity due to the need for capacitors, and NOR memory arrays experience complications with unselected cells interfering with read, write, or erase operations.
Innovation Solution
A NAND string configuration with contactless serial connections between semiconductor memory cells, utilizing a floating body region and back bias region to inject or extract charge, and a fin structure for vertical extension of the floating body region, allowing for efficient data storage and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM cells use capacitors for data storage, then data storage capability is improved, but device complexity and cell size increase
Solution Approach 1:
The patent removes the capacitor component from the memory cell structure entirely. Instead of using a capacitor to store charge, the invention utilizes the floating body region of the transistor itself to store charge through impact ionization-generated holes, thereby eliminating the need for separate capacitor structures and reducing overall device complexity
Solution Approach 2:
The transistor structure serves multiple functions: it acts as both the access device and the storage element. The floating body region of the transistor simultaneously provides the channel for charge transport and the storage medium for data retention, combining what were previously separate functions into a single integrated structure
2Ease of operation
If NOR memory arrays are used, then ease of operation is improved, but unselected cells interfere with read, write, or erase operations
Solution Approach 1:
The patent implements segmentation by dividing the memory array into isolated string structures where each string contains multiple memory cells connected in series. This segmentation allows selective access to specific strings through word lines, preventing interference between unselected cells and improving operational reliability
Solution Approach 2:
The patent introduces select transistors as intermediary devices at the ends of each memory string. These select transistors act as gatekeepers that control access to the memory cells within each string, enabling precise selection and preventing unwanted interference from unselected cells during read, write, or erase operations
3Productivity
If memory cells are scaled to smaller feature sizes, then productivity is improved, but data integrity deteriorates
Solution Approach 1:
The patent changes the fundamental parameter of charge storage mechanism by utilizing impact ionization to generate holes in the floating body region. This parameter change enables effective data storage at smaller dimensions because the impact ionization process can be reliably controlled at scaled dimensions, maintaining data integrity while enabling further scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient data storage and isolation in semiconductor memory cells, reducing interference and allowing for smaller cell sizes and improved scalability, while maintaining data integrity without the need for capacitors.
Implementation Method 1
The floating body region and back bias region are configured to perform at least one of injecting charge into or extracting charge out of the floating body region
Implementation Method 2
a back bias region configured to perform the at least one of injecting charge into or extracting charge out of the floating body region
Data Source
AI summary
NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.