Floating Body Transistor Memory Cell with Back-Bias Charge Control
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Solution Overview
Problem
Conventional semiconductor memory devices, particularly DRAM with an electrically floating body, face challenges in maintaining memory cell states without interrupting access and experiencing charge leakage during repeated read operations, requiring periodic refresh operations that can disrupt access and lead to charge loss.
Innovation Solution
A semiconductor memory cell design incorporating a floating body region, a back-bias region, and specific terminal connections that allow for the application of back bias voltage to maintain charge levels, enabling parallel holding operations and reducing charge leakage, thus allowing uninterrupted access and extended memory window capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM refresh operation is performed by reading then re-writing the memory cell, then the memory state can be maintained, but access to the memory cell is interrupted
Solution Approach 1:
The memory cell performs refresh automatically through the back-bias region injecting charge into the floating body without requiring external read-then-write operations. The floating body transistor inherently maintains its state through self-refreshing charge injection, eliminating the need for interrupting access operations.
2Productivity
If the memory cell is accessed repeatedly, then data can be read, but charge leaks from the floating body reducing stored charge
Solution Approach 1:
The back-bias region proactively injects charge into the floating body before significant charge loss occurs during repeated read operations. This preliminary charge injection compensates for the charge pumping effect that attracts floating body charge to the surface and traps it at the interface, maintaining adequate stored charge for continued operation.
3Area of stationary object
If the capacitor is eliminated in 1T-DRAM cell, then scaling to smaller feature size is easier and cell size is reduced, but charge leaks over time requiring refresh operation
Solution Approach 1:
The invention changes the charge storage mechanism from capacitor-based to floating body-based, utilizing the unique electrical properties of the floating body region. By controlling the charge state of the floating body through back-bias injection, the patent achieves both reduced cell size and improved charge retention without requiring traditional capacitors or refresh operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively maintains memory cell states without interrupting access and enhances charge retention, enabling efficient and continuous operation of semiconductor memory devices by applying back bias voltage to the back-bias region, which offsets charge leakage and increases the maximum charge storage capacity.
Implementation Method 1
a back-bias region configured to inject charge into or extract charge out of the floating body region to maintain the state of the memory cell
Implementation Method 2
a floating body region configured to be charged to a level indicative of a state of the memory cell
Implementation Method 3
applying back bias voltage to the back-bias region, which offsets charge leakage
Data Source
AI summary
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.