Floating Body Transistor Memory State Maintenance via Back Bias
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Solution Overview
Problem
Conventional DRAM memory cells with an electrically floating body require periodic refresh operations to maintain their state, which interrupts access and is affected by charge leakage during repeated read operations, necessitating methods to maintain memory cell states without interruption and reduce charge loss.
Innovation Solution
Applying a back bias to the memory cell to offset charge leakage, allowing for simultaneous access and refresh operations without interrupting memory cell access, and using a holding operation to maintain the state of memory cells by applying a constant or periodic positive voltage to the substrate terminal, enabling independent control of the bias in segmented arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic refresh operations are performed to maintain memory cell state, then memory state reliability is improved, but access continuity deteriorates due to interruption
Solution Approach 1:
The memory cell performs self-refresh by utilizing the read operation itself to maintain its state. The floating body charge is replenished during normal read operations through the inherent charge pumping effect, eliminating the need for separate refresh operations that would interrupt access.
Solution Approach 2:
The refresh function is merged with the read operation. The same circuit operations used for reading data also serve to replenish the floating body charge, combining two functions into one operation and eliminating the need for separate refresh cycles.
2Speed
If repeated read operations are performed, then data access speed is improved, but charge leakage increases causing state degradation
Solution Approach 1:
The system uses feedback from the read operation to monitor and replenish the floating body charge. The charge pumping effect during read operations provides positive feedback that compensates for charge leakage, maintaining the memory state even during repeated reads.
Solution Approach 2:
The charge leakage that normally degrades the memory state is converted into a beneficial effect. The leakage-induced potential difference drives the charge pumping mechanism that replenishes the floating body charge, turning a harmful effect into a self-correcting mechanism.
3Quantity of substance
If conventional 1T/1C structure is used, then charge storage capacity is improved, but device scalability deteriorates due to larger cell size
Solution Approach 1:
The external capacitor is extracted and replaced by the floating body region of the transistor itself. The floating body serves as the charge storage element, eliminating the need for a separate capacitor and reducing the cell size while maintaining charge storage capacity.
Solution Approach 2:
The floating body transistor serves multiple functions: it acts as both the access transistor and the charge storage element. This multi-functionality eliminates the need for separate capacitor components and enables smaller cell sizes while maintaining DRAM functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains memory cell states without interrupting access, reduces charge leakage, and increases the maximum charge storage capacity, allowing for uninterrupted operations and improved memory window size in semiconductor memory devices.
Implementation Method 1
applying a back bias to the cell to offset charge leakage out of a floating body of the cell
Implementation Method 2
a charge level of the floating body indicates a state of the memory cell
Data Source
AI summary
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.