Floating Body Transistor U-Shaped Fin Memory Integration
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Solution Overview
Problem
Traditional memory devices, such as SRAM and DRAM, face challenges in achieving high integration and low power consumption, with DRAM capacitors becoming too large for next-generation levels, prompting the need for a capacitor-less DRAM solution that utilizes a floating body of a partially or fully depleted silicon on insulator (SOI) field effect transistor as a storage node.
Innovation Solution
The development of floating body transistor constructions where source and drain lines are laid out along prongs of a U-shaped semiconductor fin, enabling high scalability and data retention, and the formation of memory arrays using these cells, which can be integrated into semiconductor fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DRAM with capacitor is used, then data storage function is achieved, but semiconductor real estate consumption increases and integration level decreases
Solution Approach 1:
The patent extracts and removes the capacitor component from the traditional DRAM structure, replacing it with a floating body transistor that uses the body region of the transistor itself as the storage node. This extraction eliminates the need for separate capacitor structures, thereby reducing semiconductor real estate consumption while maintaining data storage functionality.
Solution Approach 2:
The patent merges the storage function with the transistor structure by using the transistor's body region as the floating storage node. This combining of the storage function into the existing transistor architecture eliminates the need for separate capacitor components, achieving higher integration density while preserving data storage capability.
2Speed
If SRAM is used for high-speed operation, then speed performance is improved, but semiconductor real estate consumption increases
Solution Approach 1:
The patent changes the operational parameters and structure of the memory cell by using a floating body transistor with controlled depletion regions. This allows the cell to operate at high speeds similar to SRAM while consuming less area, as the floating body structure enables rapid charge/discharge cycles without requiring the complex six-transistor SRAM architecture.
3Productivity
If DRAM capacitor size is reduced for higher integration, then integration level improves, but capacitor fabrication difficulty increases
Solution Approach 1:
The patent removes the capacitor component entirely from the memory cell structure, replacing it with a floating body transistor. This extraction eliminates the fabrication challenges associated with miniaturized capacitors, as the floating body structure can be formed using standard transistor fabrication processes without requiring specialized capacitor manufacturing techniques.
Solution Approach 2:
The floating body transistor structure serves multiple functions: it acts as both the transistor switch and the storage element. This multi-functionality eliminates the need for separate capacitor fabrication processes, allowing the same transistor fabrication techniques to create both the switching element and the storage node, thereby simplifying manufacturing.
Data Source
AI summary
The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.