Floating-bridge Interconnects for High-density Semiconductor Packaging
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Solution Overview
Problem
The miniaturization of semiconductive devices during packaging requires 2D multiple-die footprints, which poses challenges in achieving higher chipset densities and efficient interconnectivity while managing inductive and resistivity issues.
Innovation Solution
The implementation of floating-bridge interconnects, specifically silicon-bridge and organic-bridge interconnects, which hover above a middle semiconductive device, allowing for high-speed interconnectivity between logic processors and graphics processors without requiring additional lateral connections, thus optimizing package-substrate real estate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D multiple-die footprints are used for miniaturization, then device density is improved, but inductive and resistivity issues worsen
Solution Approach 1:
The patent transitions from traditional 2D planar interconnects to 3D vertically-stacked interconnect bridges. Multiple interconnect bridges are stacked vertically above the middle semiconductive device, creating a three-dimensional architecture that enables faster signal transmission and reduces inductive and resistivity effects while maintaining high device density.
2Adaptability or versatility
If lateral connections are added for interconnectivity, then connectivity is improved, but package-substrate real estate is consumed
Solution Approach 1:
The patent employs vertical stacking of interconnect bridges in the Z-dimension rather than expanding lateral connections in the X-Y plane. This 3D architecture provides multiple interconnect pathways between logic processors and graphics processors without consuming additional package-substrate real estate, effectively resolving the space-connectivity tradeoff.
3Speed
If interconnect bridges are stacked vertically, then interconnect speed is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms multiple interconnect bridges in a stacked configuration before final assembly, with bridge contact pads and device contact pads pre-positioned and aligned. This preliminary structuring simplifies subsequent assembly steps and reduces manufacturing complexity despite the 3D architecture.
Solution Approach 2:
The patent introduces a middle semiconductive device as an intermediary platform that supports the vertically-stacked interconnect bridges. This middle device serves as a foundation for the 3D interconnect structure, enabling complex vertical stacking while maintaining manufacturing feasibility through modular assembly.
Data Source
AI summary
A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.