Floating-Bulk PMOS Logic Circuit for Leakage Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
PMOS transistors in logic circuits experience leakage current due to the operating voltage exceeding their breakdown voltage when turned off, leading to inefficiencies and potential damage.
Innovation Solution
The logic circuit design includes PMOS and NMOS transistors with floating bulk voltages, ensuring that the voltage difference between the bulk and drain does not exceed the breakdown voltage, thereby preventing leakage current and maintaining transistor functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PMOS transistor bulk is coupled to the operating voltage, then the transistor can be turned off properly, but leakage current occurs when the operating voltage exceeds the breakdown voltage
Solution Approach 1:
The bulk voltage is made dynamic rather than fixed at the operating voltage. The bulk voltage automatically adjusts based on the drain voltage through the series coupling configuration, ensuring that the bulk-drain voltage difference never exceeds the breakdown voltage, thus preventing leakage current while maintaining proper transistor operation
Solution Approach 2:
The invention changes the bulk voltage parameter from a fixed operating voltage to a floating voltage that dynamically adapts to the drain voltage. This parameter change ensures that the bulk-drain voltage difference remains within safe limits, preventing breakdown and leakage current while maintaining transistor functionality
2Object-generated harmful factors
If the PMOS transistor bulk is left floating, then leakage current is prevented, but the transistor may not turn off properly
Solution Approach 1:
The series-coupled PMOS transistor acts as an intermediary that controls the bulk voltage of the first PMOS transistor. By adjusting its own bulk voltage based on the drain voltage, it mediates between the need for a floating bulk (to prevent leakage) and the need for proper off-state performance, ensuring both requirements are met simultaneously
Data Source
AI summary
A logic circuit including a first PMOS transistor, a second PMOS transistor, and an NMOS transistor is provided. The first PMOS transistor is coupled to an input-output pad. The second PMOS transistor is coupled to the first PMOS transistor in series between the input-output pad and an output terminal and receives a first input signal. The NMOS transistor is coupled to the second PMOS transistor. The voltage of the bulk of the first PMOS transistor is a first floating level. The voltage of the bulk of the second PMOS transistor is a second floating level.