Floating Buried Layer Architecture for High Voltage Breakdown
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Solution Overview
Problem
Advanced CMOS integrated circuits face challenges in integrating high voltage components due to premature breakdown and shortened operating lifetimes, as they require junctions with wide depletion regions and shallow doping gradients, which are difficult to achieve without compromising dimensional stability and increasing area.
Innovation Solution
The implementation of a buried layer architecture with a floating buried layer structure adjacent to the buried layer, allowing for increased breakdown potentials up to 140 volts without area expansion, achieved by incorporating one or more floating buried layer structures in high voltage devices like DEPMOS, LDMOS, and CMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long anneals of ion implanted regions at high temperatures are used to achieve wide depletion regions and shallow doping gradients, then breakdown potential is improved, but dimensional stability deteriorates
Solution Approach 1:
The patent divides the single buried layer into multiple segments: a contacted buried layer and one or more floating buried layer structures. This segmentation allows each layer to serve specific functions - the contacted layer provides electrical connection while floating layers extend the depletion region - achieving high breakdown potential without requiring long anneals that would compromise dimensional stability
Solution Approach 2:
The patent transitions from a single-plane buried layer configuration to a multi-layer vertical stacking architecture. By adding floating buried layer structures at different depths and positions, the depletion region is extended in the vertical dimension, enabling high breakdown potential while maintaining the horizontal dimensional stability required for advanced CMOS fabrication
2Reliability
If deep well regions are added around buried layers to increase breakdown potentials, then breakdown potential is improved, but area increases
Solution Approach 1:
The patent embeds floating buried layer structures within or adjacent to the contacted buried layer configuration, creating a nested multi-layer structure. This nesting approach extends the depletion region vertically and laterally without requiring expansion of the overall device footprint, thus increasing breakdown potential while maintaining compact area
3Loss of energy
If high doping densities are used in buried layers for low electrical resistances, then electrical resistance is reduced, but breakdown potential deteriorates
Solution Approach 1:
The patent applies different doping densities to different buried layer structures: the contacted buried layer uses high doping density to minimize contact resistance, while floating buried layer structures use lower doping densities to extend the depletion region and increase breakdown potential. This local differentiation allows simultaneous optimization of both electrical resistance and breakdown characteristics
Data Source
AI summary
A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.