Floating Buried Layer Ring for IC Isolation
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Solution Overview
Problem
Conventional integrated circuits face degraded avalanche breakdown between buried layers in high-voltage and low-voltage devices due to proximity, leading to electrostatic discharge (ESD) issues and compromised breakdown voltage.
Innovation Solution
Incorporation of a vertical diode ring with a floating buried layer and a pwell between the isolated island and the high-voltage tank, which acts as a spacer to maintain isolation and prevent premature breakdown, while adhering to stringent ESD layout rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the spacing between the buried layer in the island and the buried layer in the HV tank is reduced to satisfy ESD layout rules, then the ESD tolerance is improved, but the avalanche breakdown voltage is degraded due to bipolar snapback
Solution Approach 1:
A floating buried layer is introduced as an intermediary structure between the island buried layer and the HV tank buried layer. This floating buried layer acts as a mediator that prevents direct interaction between the two buried layers, thereby maintaining the ESD layout spacing requirements while preserving the avalanche breakdown voltage through the formation of a vertical diode ring structure with a pwell on top
2Strength
If a larger spacing is maintained between the buried layers, then the avalanche breakdown voltage is preserved, but the ESD layout rule is violated
Solution Approach 1:
The solution transitions from a two-dimensional lateral spacing approach to a three-dimensional vertical structure by forming a floating buried layer that extends upward to create a vertical diode ring with a pwell on top. This dimensional change allows the buried layers to be positioned closer laterally while maintaining electrical isolation through the vertical structure, thus satisfying both ESD layout rules and breakdown voltage requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides robust isolation and maintains vertical voltage blocking capability, enabling operation at higher voltages without compromising ESD tolerance, thus enhancing the integration of high-voltage and low-voltage devices on the same IC chip.
Implementation Method 1
the breakdown voltage from devices at the edge of the island to the HV tank generally decreases as this spacing decreases
Data Source
AI summary
An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of semiconductor devices formed in the semiconductor surface having a first n-buried layer (NBL) thereunder. A vertical diode formed in the semiconductor surface surrounds the first nwell including a pwell on top of a floating NBL ring. A second nwell formed in the semiconductor surface includes an area surrounding the floating NBL ring and surrounds a second plurality of semiconductor devices having a second NBL thereunder.