SAR ADC Charge Redistribution for Large Input Range
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Solution Overview
Problem
Current successive approximation register (SAR) analog-to-digital converters (ADCs) face a challenge in achieving a high signal-to-noise ratio (SNR) due to the need to divide input signals, which reduces the SNR and requires high-voltage transistors to handle large input voltage ranges, especially when operating with a 5 V supply voltage.
Innovation Solution
The method involves using a set of capacitors where one side of each capacitor is coupled to a common node, with some capacitors left floating during initial bit decisions, allowing charge redistribution between these capacitors and others, thereby reducing the need for initial signal division and enhancing SNR by activating additional charge during later conversion steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the input signal is divided to fit the ADC input range, then the input voltage range can be handled, but the signal-to-noise ratio decreases
Solution Approach 1:
The capacitor array is divided into two separate arrays: a first capacitor array that samples the full input voltage range without division, and a second capacitor array that operates with divided voltage for standard ADC conversion. This segmentation allows each array to specialize in different voltage handling, preserving the full signal amplitude in the first array to maintain SNR while the second array handles the conversion process
Solution Approach 2:
A voltage divider circuit acts as an intermediary between the full-range input signal and the ADC core. The voltage divider scales down the input voltage for the second capacitor array and ADC conversion, while the first capacitor array directly captures the full-range signal. This intermediary approach allows the system to handle large input voltages without degrading the signal-to-noise ratio
2Adaptability or versatility
If high-voltage transistors are used to handle large input voltage ranges, then the input range can be expanded, but the die size and power consumption increase
Solution Approach 1:
The system segments the voltage handling function between two capacitor arrays: the first array handles high-voltage sampling with standard transistors by capturing the full input range, while the second array operates at reduced voltage levels for the conversion process. This segmentation allows standard 5V transistors to be used throughout, eliminating the need for area-consuming high-voltage transistors while maintaining the ability to handle large input voltage ranges
3Reliability
If signal division is implemented to adapt to comparator input range, then the ADC can operate within supply voltage limits, but the achievable signal-to-noise ratio is reduced
Solution Approach 1:
The capacitor arrays are segmented into two functional groups: the first array directly samples the full input signal without division, preserving signal amplitude and SNR, while the second array implements the necessary voltage division for comparator operation. This segmentation allows the system to maintain high SNR in signal capture while ensuring reliable comparator operation through controlled division in the conversion stage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the signal-to-noise ratio by at least 12 dB compared to prior art, allowing for efficient analog-to-digital conversion with reduced noise levels and enabling the use of standard 5 V transistors, which decreases die size and power consumption.
Implementation Method 1
capacitive DACs (CDACs) are often used, which include a plurality of capacitors. The analog input voltage can be sampled directly on the capacitors of the CDAC, such that a charge corresponding to the size of the capacitors and proportional to the amplitude of the input voltage is present on the sampling capacitors
Implementation Method 2
The sampled charge is redistributed stepwise among the capacitors of the CDAC. The capacitors are connected together on one side to a common node. The magnitude of the input voltage is basically determined by selectively and consecutively switching the other sides of the capacitors between different reference voltage levels and comparing the established voltage level on the common node to a mid voltage level
Data Source
AI summary
A method for analog-to-digital conversion is provided using successive approximation and a plurality of capacitors including a first set of capacitors and a second set of capacitors, a first side of each of the plurality of capacitors being coupled to a common node. The method includes sampling an input voltage on the first set of capacitors, after the step of sampling leaving a side of at least one capacitor of the first set of capacitors floating, coupling a capacitor of the first set of capacitors, which is not floating, with a capacitor of the second set of capacitors so as to redistribute the charge on the coupled capacitors, comparing the voltage on the common node with a comparator reference voltage level to receive a comparison result to be used for a bit decision, and switching the floating side of the floating capacitor of the first set of capacitors to either a first reference voltage or a second reference voltage in accordance with the bit decision.