Floating Comparator Input Stage for Wide Common-Mode Voltage
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Solution Overview
Problem
Existing driver topologies face challenges in expanding the common mode range (CMR) to accommodate large voltage differences between signal ground and device ground, leading to increased circuit complexity and reduced signal path speed due to the need for bi-directional ESD structures and on-chip trimming.
Innovation Solution
A driver with a floating input stage (FIS) that provides a DC voltage offset to decouple the differential input pair from the device ground, dynamically adjusts the reference voltage to track input signal variations, and mitigates negative voltage impacts without bi-directional ESD structures or on-chip trimming, thereby expanding the CMR and reducing propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bi-directional ESD structures and on-chip trimming are used to expand common mode range, then the driver can accommodate large voltage differences between SGND and GND, but circuit complexity increases and signal path speed decreases
Solution Approach 1:
The patent removes bi-directional ESD structures and on-chip trimming components from the circuit. The floating input stage directly couples to SGND without requiring additional protection or calibration components, thereby reducing circuit complexity while maintaining wide common mode range through the inherent flexibility of the floating input architecture
Solution Approach 2:
The input stage is segmented into a floating differential pair configuration that is electrically isolated from GND and directly referenced to SGND. This segmentation allows each part of the input stage to operate independently within its own voltage domain, enabling wide common mode range without requiring complex inter-component coordination or trimming circuits
2Adaptability or versatility
If bi-directional ESD structures and on-chip trimming are used to expand common mode range, then the driver can accommodate large voltage differences between SGND and GND, but signal path speed decreases due to increased propagation delays
Solution Approach 1:
The patent removes on-chip trimming components and associated calibration circuitry from the signal path. By eliminating these additional components, the signal propagation path is shortened and simplified, reducing the number of potential delay points while maintaining wide common mode range through the floating input stage's direct SGND reference
Solution Approach 2:
The floating input stage is pre-configured with direct SGND coupling and appropriate biasing through the voltage divider network, eliminating the need for post-manufacturing trimming or calibration. This preliminary configuration ensures optimal signal path performance is achieved directly from fabrication, reducing propagation delays without sacrificing common mode range
3Adaptability or versatility
If voltage divider pair is used to create stepped down common mode voltage, then common mode range is expanded, but negative voltages appear on driver input requiring bi-directional ESD structures
Solution Approach 1:
The patent introduces a floating input stage as an intermediary between the controller output and the differential input pair. This floating stage is directly coupled to SGND and isolated from GND, acting as a mediator that references all input signals to SGND rather than GND. This eliminates negative voltage appearance on the driver input while maintaining expanded common mode range, as the floating input stage naturally accommodates large SGND-to-GND voltage differences without requiring bi-directional ESD protection
Solution Approach 2:
The floating input stage and differential input pair are held at the same SGND reference potential through direct coupling. By establishing equipotential conditions between the input stage and SGND, the patent eliminates potential differences that would otherwise create negative voltage conditions requiring ESD protection, while the voltage divider network maintains the ability to handle large common mode voltage swings
Data Source
AI summary
An apparatus includes a differential input pair, a first resistor, a second resistor, and a comparator. The differential input pair having first and second differential inputs. The first differential input is adapted to be coupled to an output of a controller and the second differential input is adapted to be coupled to a signal ground of the controller. The first resistor is adapted to be coupled to a third resistor via the first differential input to form a first voltage divider. The second resistor is adapted to be coupled to a fourth resistor via the second differential input to form a second voltage divider. The comparator having first and second comparator inputs. The first comparator input is coupled between the first resistor and the first differential input. The second comparator input is coupled between the second resistor and the second differential input.