Floating Conductive Layer Memory Suppressing Standby Leak Current
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Solution Overview
Problem
Conventional crosspoint diode ROMs experience leak currents during standby time due to precharged conductive layers and grounded bit lines, which affects data retention and evaluation of leak phenomena, requiring inefficient testing procedures.
Innovation Solution
The memory design features conductive layers and bit lines in floating states during standby, with transistors connected to bit lines entering ON-states for evaluating leak phenomena, reducing leak currents and testing time by precharging conductive layers and adjusting bit line potentials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive layers are precharged to high level and bit lines are grounded in standby time, then data can be retained in memory cells, but leak current increases
Solution Approach 1:
The patent inverts the conventional standby state configuration: instead of grounding bit lines and precharging conductive layers (which causes leak current), it precharges bit lines to high level and leaves conductive layers in floating state. This inversion eliminates the leak current path while maintaining data retention capability through the diode's charge storage property.
Solution Approach 2:
The patent changes the electrical parameters of the standby state: bit line potential is changed from ground (0V) to precharged high level, and conductive layer state is changed from precharged to floating. This parameter change transforms the system from a state with high leak current to a state with minimal leak current while preserving functionality.
2Measurement precision
If conventional testing procedures are used to evaluate leak phenomena, then leak current can be measured, but testing time is excessive
Solution Approach 1:
The patent applies preliminary action by precharging bit lines to high level before conducting leak current evaluation. This preliminary preparation creates optimal conditions for leak current measurement, allowing the evaluation to be completed in a single operation without requiring prolonged testing periods or multiple measurement steps.
Solution Approach 2:
The patent enables rushing through the leak current evaluation process by utilizing the precharged bit lines and floating conductive layers configuration, which naturally exhibits leak current characteristics. This allows the evaluation to be completed quickly without waiting for prolonged standby periods or performing iterative measurements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design suppresses leak currents, simplifies the memory cell array structure, and reduces the time required for evaluating leak phenomena, enhancing data retention and testing efficiency.
Implementation Method 1
utilizing a charge storage property of the diode
Data Source
AI summary
A memory includes conductive layers provided to extend along the word lines, memory cells each including a diode having a cathode connected to the conductive layer and a source line reading data stored in the memory cells, wherein either the conductive layers or the bit lines are in floating states in a standby time.