Floating Contact Plug Layout to Prevent Dummy Gate Conduction
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Solution Overview
Problem
Current semiconductor fabrication methods for poly-gate or high-k metal transistors often result in contact plugs that induce conduction in dummy gates, leading to circuit failure.
Innovation Solution
The method involves forming a semiconductor device with active devices, an interlayer dielectric (ILD) layer, and floating contact plugs. These floating contact plugs are formed by creating contact holes in the ILD layer without exposing the active device, and then filling these holes with a metal layer, ensuring that the bottom surface of the contact plugs is higher than the top surface of the gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed in the later stage to connect to gate structures or source/drain region, then connectivity is achieved, but conduction is induced in the original dummy gate causing circuit failure
Solution Approach 1:
The contact plug is segmented into two distinct parts: a first contact plug portion extending from the upper surface of the interlayer dielectric layer to a height between the upper surface of the gate structure and the upper surface of the source/drain region, and a second contact plug portion extending from the upper surface of the interlayer dielectric layer to the upper surface of the source/drain region. This segmentation prevents conduction in the dummy gate while maintaining connectivity to the source/drain region.
Solution Approach 2:
Different portions of the contact plug are positioned at different heights to perform different functions. The first contact plug portion is positioned to avoid shorting the dummy gate, while the second contact plug portion provides the necessary electrical connection to the source/drain region. This local differentiation in position and function resolves the contradiction between connectivity and preventing harmful conduction.
2Manufacturing precision
If contact holes are formed without exposing the active device, then the active device is protected, but the bottom surface of the contact hole must be positioned at a specific height
Solution Approach 1:
The contact holes are formed through the interlayer dielectric layer before the final planarization step, with the bottom surface of the contact holes positioned at a predetermined height between the upper surface of the gate structure and the upper surface of the source/drain region. This preliminary positioning allows subsequent planarization to expose the contact holes while protecting the active device, achieving both precision and simplified fabrication.
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of first forming an active device having a gate structure and a source/drain region on a substrate, forming an interlayer dielectric (ILD) layer on the active device, removing part of the ILD layer to form a contact hole on the active device without exposing the active device and the bottom surface of the contact hole is higher than a top surface of the gate structure, and then forming a metal layer in the contact holt to form a floating contact plug.