Stacked Image Sensor Wiring Capacitance for High-Illuminance Dynamic Range
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Solution Overview
Problem
Imaging devices with three-dimensional structures face challenges in extending dynamic range due to reduced pixel transistor working range and increased noise, especially in high illuminance conditions, where fine pixels have limited space for wiring and capacitance addition, limiting the ability to handle high saturation signals effectively.
Innovation Solution
The implementation of a wiring layer configuration with electrically coupled first and second wiring lines between stacked semiconductor substrates, where one line is in an electrically floating state and the other is coupled to a transistor, increases the capacitance of the floating diffusion, allowing for variable capacitance and improved signal handling by routing capacitance addition wiring lines within the lower wiring layer on the first substrate, thereby enhancing dynamic range without increasing the number of steps or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pixels are used to achieve higher pixel density, then pixel density is improved, but the working range of pixel transistors is reduced and noise increases
Solution Approach 1:
The patent moves the capacitance addition function from the planar dimension to the vertical dimension by stacking a second semiconductor substrate on the first substrate. This three-dimensional configuration allows capacitance wiring to be added without increasing the in-pixel wiring area, thus maintaining high pixel density while extending the transistor working range through increased floating diffusion capacitance.
2Reliability
If capacitance is increased to extend dynamic range, then dynamic range is improved, but wiring area and device complexity increase
Solution Approach 1:
The patent utilizes the vertical dimension by stacking a second semiconductor substrate on the first substrate. This allows capacitance addition wiring to be routed in the vertical direction rather than consuming additional planar wiring area, thereby extending dynamic range without increasing wiring complexity in the two-dimensional plane.
Solution Approach 2:
The patent creates a stacked configuration where the second substrate mirrors the functional structure of the first substrate, with readout circuits on the second substrate corresponding to sensor pixels on the first substrate. This copying approach allows capacitance wiring to be added in the vertical dimension without increasing in-pixel wiring complexity.
3Reliability
If more wiring lines are added to increase capacitance, then capacitance is improved, but manufacturing steps and cost increase
Solution Approach 1:
The patent merges the capacitance addition function with the existing stacked substrate structure. By integrating capacitance wiring into the vertical interconnect structure between substrates, the design adds capacitance functionality without requiring separate manufacturing steps or additional wiring layers beyond the standard stacked configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows the imaging device to handle larger signal amounts and extend the dynamic range by increasing the capacitance of the floating diffusion, improving signal handling and reducing noise, even in high illuminance conditions, while maintaining a compact design.
Implementation Method 1
a sensor pixel that performs photoelectric conversion
Implementation Method 2
The wiring layer is provided between the first semiconductor substrate and the second semiconductor substrate and includes a first wiring line and a second wiring line that are electrically coupled to each other... This increases the wiring capacitance
Data Source
AI summary
An imaging device including: a first semiconductor substrate; a second semiconductor substrate; and a wiring layer. The first semiconductor substrate has a first surface and a second surface and includes a sensor pixel. The second semiconductor substrate has a third surface and a fourth surface and includes a readout circuit that outputs a pixel signal based on an output from the sensor pixel. The second semiconductor substrate is stacked on the first semiconductor substrate with the first surface and the fourth surface opposed to each other. The wiring layer is between the first semiconductor substrate and the second semiconductor substrate and includes a first wiring line and a second wiring line that are electrically coupled to each other. One of the first wiring line and the second wiring line is in an electrically floating state while the other is electrically coupled to a transistor.