Floating Diode Structure for Bidirectional Bias and Parasitic Control
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Solution Overview
Problem
In integrated circuit designs, semiconductor diodes require pre-selection of bias direction, leading to design constraints and issues like unwanted currents, latch-up phenomena, and noise due to parasitic diode activation, especially in high-voltage applications where adverse conditions like voltage spikes and battery reversal occur.
Innovation Solution
A floating diode structure is formed adjacent a high-doped bulk semiconductor substrate with a buried layer that reduces current injection into the substrate, allowing for both positive and negative biasing and minimizing parasitic effects, using a doped region configuration that includes a floating doped layer and buried layers with specific dopant concentrations to manage current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If pre-selection of bias direction is required for diode operation, then parasitic diode activation is avoided, but design flexibility is reduced and external diodes or SOI technologies are needed
Solution Approach 1:
The device is segmented into distinct functional regions: a first doped region (N-type) and a second doped region (P-type) that are laterally adjacent and both contact the substrate, creating separate parasitic diode structures. This segmentation allows each region to independently form diode junctions with the substrate, enabling the device to handle both positive and negative voltage transients without requiring pre-selected bias direction.
Solution Approach 2:
The device structure provides multi-functionality by enabling operation in multiple bias modes (positive bias, negative bias, and unbiased) through its symmetric doped region configuration. The first and second doped regions can each serve as either anode or cathode depending on the applied voltage polarity, making the device adaptable to various operating conditions without requiring external components or complex bias selection circuits.
2Adaptability or versatility
If external diodes are used to solve bias issues, then design flexibility is improved, but cost, pin count, and PCB space increase
Solution Approach 1:
The patent merges the functions of multiple components into a single integrated device structure. The first and second doped regions, along with their respective electrodes, are combined into one device that can independently handle both positive and negative voltage transients. This eliminates the need for external diodes, reducing component count, PCB space requirements, and overall system complexity while maintaining bias adaptability.
Solution Approach 2:
The integrated device structure provides universal protection against both positive and negative voltage transients within a single component footprint. The symmetric configuration of doped regions allows the device to function as either a standard diode or a bidirectional transient voltage suppressor, replacing multiple external components with one multi-functional device that reduces BOM cost and assembly complexity.
3Adaptability or versatility
If SOI technology is used to enable positive and negative biasing, then design flexibility is improved, but manufacturing complexity and thermal resistance increase
Solution Approach 1:
The patent applies local quality by creating a substrate contact structure with specific doping characteristics in the region where the first and second doped regions meet the substrate. The substrate contact is doped to form low-impedance contact with the substrate, while the first and second doped regions maintain their respective doping concentrations to form parasitic diode junctions. This localized doping strategy enables positive and negative biasing without requiring complex SOI technology, maintaining manufacturing simplicity.
Solution Approach 2:
The patent utilizes parameter changes in doping concentrations to achieve the desired electrical characteristics. By adjusting the doping concentrations of the first doped region, second doped region, and substrate contact, the device can operate in multiple bias modes. The substrate contact is doped at a concentration that ensures low-impedance contact, while the doped regions are doped at concentrations that optimize the parasitic diode junctions, enabling flexible bias operation without changing the fundamental bulk substrate architecture.
4Object-generated harmful factors
If doped regions are configured to reduce current injection into substrate, then parasitic effects are minimized, but device structure complexity increases
Solution Approach 1:
The patent applies local quality by creating a substrate contact with specific doping characteristics that is laterally adjacent to but separate from the first and second doped regions. The substrate contact is doped to form a low-impedance path to the substrate, while the first and second doped regions are doped at concentrations that optimize their parasitic diode junctions. This localized differentiation in doping strategy minimizes current injection into the substrate while maintaining a relatively simple overall device structure that can be fabricated using standard semiconductor processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The floating diode structure enhances design flexibility and performance by enabling unbiased operation, reducing parasitic injection and thermal resistance, and maintaining low current leakage across various bias modes, thus improving reliability and efficiency in adverse conditions.
Implementation Method 1
The floating doped region includes a buried layer having a doping concentration that reduces current injection into the high-doped bulk semiconductor substrate
Data Source
AI summary
In one embodiment, a floating diode structure includes a p-type semiconductor substrate. An n-type doped region is disposed between the semiconductor substrate and a p-type doped region of the first conductivity type adjacent the first doped region. An n-type cathode region is disposed within the p-type doped region and a p-type anode region is disposed within the cathode region. An anode electrode is connected to the anode region and a cathode electrode is connected to the cathode region. In one embodiment, the cathode electrode is further connected to the p-type doped region. The n-type doped region is configured as a floating region that facilitates the diode operating in both a forward and reverse bias mode and both below ground and above ground with respect to the p-type semiconductor substrate.