Floating Deep N-Well Low Noise Amplifier Gain
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Solution Overview
Problem
Millimeter-wave low noise amplifiers (LNAs) implemented using compound III-V semiconductors or BJTs face integration challenges with digital circuits, leading to higher implementation costs, and existing CMOS technologies require multi-stage LNAs for sufficient amplification.
Innovation Solution
The implementation of a low noise amplifier with a floating deep n-well (DNW) in transistors, which reduces source degeneration and body effect, improving gain performance by isolating the n-well from the source using isolation circuits such as resistors, quarter-wavelength transmission lines, or LC tanks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If compound III-V semiconductors or BJTs are used for LNA implementation, then gain performance is improved, but integration with digital circuits becomes difficult and implementation cost increases
Solution Approach 1:
The patent changes the material parameter from compound III-V semiconductors or BJTs to CMOS technology, achieving sufficient gain performance through optimized transistor design with floating deep n-well structures while maintaining compatibility with standard digital circuit fabrication processes
Solution Approach 2:
The LNA is designed to operate within the standard CMOS process framework, allowing the same fabrication facility to produce both digital circuits and RF analog circuits, thereby achieving multi-functionality and reducing implementation costs
2Ease of manufacture
If multi-stage LNAs are implemented using CMOS technology, then integration with digital circuits is improved, but device complexity increases
Solution Approach 1:
The LNA is divided into multiple stages with distinct functions: first stage for low-noise amplification with optimized input matching, second stage for gain enhancement with intermediate matching, and output stage for power delivery, allowing each segment to be optimized independently while maintaining overall system performance
Solution Approach 2:
Intermediate matching networks and isolation circuits are introduced between stages to decouple the design of each stage, allowing independent optimization of noise figure, gain, and output power without requiring complex simultaneous optimization of the entire multi-stage system
3Ease of manufacture
If standard CMOS transistors are used, then manufacturing cost is reduced, but source degeneration and body effect reduce gain performance
Solution Approach 1:
The deep n-well is extracted and isolated from the substrate using isolation circuits, removing the source of body effect and allowing the transistor to operate with improved gain performance while maintaining CMOS compatibility and low manufacturing cost
Solution Approach 2:
Standard CMOS transistors with simple structure are used instead of expensive specialized devices, accepting the inherent limitations of standard transistors but compensating through circuit-level optimizations including floating well configuration and matching networks
Data Source
AI summary
A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit.