Floating Dopant Isolation for LDMOS Breakdown Margin
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Solution Overview
Problem
The scaling of semiconductor device sizes to smaller dimensions poses challenges in maintaining breakdown-free operation for laterally-diffused metal-oxide-semiconductor (LDMOS) transistors, particularly in reducing the space required for dual junction isolation structures.
Innovation Solution
Incorporating a dopant isolation region that is electrically floating, laterally surrounding the drain region and counter-dopant isolation region, which reduces the distance between these regions and prevents electrical shorting, thereby minimizing the footprint and likelihood of breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation structures are used in LDMOS transistors, then breakdown-free operation is ensured, but the device footprint becomes large
Solution Approach 1:
The isolation structure is divided into multiple doped regions (first dopant isolation region and second dopant isolation region) with different conductivity types, creating segmented isolation zones that provide breakdown protection while reducing overall footprint
Solution Approach 2:
Different regions are doped with different conductivity types (first dopant and second dopant) to create localized electrical properties that optimize both isolation effectiveness and space efficiency in different areas of the device
2Productivity
If device dimensions are scaled down, then integration density increases, but breakdown risk in isolation structures increases
Solution Approach 1:
The dopant concentration parameters are optimized with the first dopant isolation region having a concentration between 1×10^16 to 1×10^18 atoms/cm³ and the second dopant isolation region having a concentration between 1×10^18 to 1×10^20 atoms/cm³, enabling compact dimensions while maintaining breakdown resistance
Solution Approach 2:
The isolation structure extends in multiple spatial dimensions with the first dopant isolation region laterally surrounding the drain region and the second dopant isolation region laterally surrounding the first dopant isolation region, providing three-dimensional isolation that maintains effectiveness at smaller planar dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a reduced transistor footprint while maintaining breakdown margin, with dimensions between regions decreased to prevent substrate breakdown, enhancing operational efficiency and reliability.
Implementation Method 1
The first dopant isolation region is doped with a second dopant conductivity type opposite from the first dopant conductivity type. The first dopant isolation region is an electrically floating node.
Implementation Method 2
dual junction isolation structures, e.g., back-to-back diodes. While such embodiments may be expected to reduce the space needed to ensure breakdown-free operation of such isolation structures
Data Source
AI summary
The present disclosure generally relates to isolation of a semiconductor device formed in a semiconductor substrate. In an example, a semiconductor device includes a drift well, a drain region, a first dopant isolation region, and a second dopant isolation region. The drift well, drain region, first dopant isolation region, and second dopant isolation region are disposed in a semiconductor substrate. The drift well, drain region, and second dopant isolation region are doped with a first dopant conductivity type. The first dopant isolation region is doped with a second dopant conductivity type opposite from the first dopant conductivity type. The drain region is disposed within the drift well. The first dopant isolation region circumscribes the drain region. The first dopant isolation region is an electrically floating node. The second dopant isolation region circumscribes the first dopant isolation region.