Floating Gate Alignment in Flash Memory Manufacturing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high-voltage operations in flash memory devices, such as third generation embedded super-flash memory cells, lead to deep source/drain region implants, causing current crowding and potential manufacturing challenges, particularly in forming uniform floating gates and maintaining yield rates.
Innovation Solution
A method for manufacturing semiconductor devices involves forming floating gates and control gates over recessed regions of a substrate, using specific etching processes and mask layers to create aligned features, which reduces voids between floating gates and isolation features, and allows for the formation of memory stacks without planarizing the floating gates, thereby improving thickness uniformity and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep source/drain region implants are performed to enable high-voltage operations in flash memory devices, then the device can achieve higher voltage tolerance, but current crowding occurs and manufacturing precision deteriorates
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming isolation features with specific depths, depositing floating gate material, and selectively removing portions. The isolation features are segmented at different depths (first depth for cell region, second depth for peripheral region), allowing precise control over floating gate formation and preventing current crowding while maintaining voltage tolerance.
Solution Approach 2:
The patent performs preliminary actions by forming isolation features before depositing the floating gate material. The isolation features are pre-formed at specific depths to define the regions where floating gate material will be retained or removed. This preliminary structuring ensures that when floating gate material is deposited and subsequently processed, uniform thickness is achieved without current crowding, while still enabling the high-voltage operations needed for reliability.
2Ease of manufacture
If conventional manufacturing processes are used for forming floating gates, then existing process flows can be maintained, but floating gate dishing and erosion occur reducing yield
Solution Approach 1:
The patent performs preliminary formation of isolation features at two different depths before depositing floating gate material. This preliminary structuring creates a template that guides subsequent material deposition and removal, ensuring uniform floating gate thickness without dishing or erosion. The process maintains continuity with existing manufacturing flows while achieving superior precision.
Solution Approach 2:
The patent applies local quality by creating isolation features with different depths in different regions: cell region isolation features extend to a first depth while peripheral region isolation features extend to a second depth. This localized differentiation allows precise control over where floating gate material is retained or removed, preventing dishing and erosion in critical areas while maintaining ease of manufacture through a unified process approach.
3Manufacturing precision
If additional photomasks are used for hard mask removal and isolation feature recessing, then manufacturing precision can be improved, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent applies universality by designing a single photomask pattern that serves multiple functions: it defines both the hard mask removal regions and the isolation feature recessing regions. This multi-functional photomask achieves precise alignment for both operations without requiring additional masks, thereby reducing device complexity and manufacturing costs while maintaining manufacturing precision through the unified patterning approach.
Data Source
AI summary
A semiconductor device includes a substrate, an isolation feature, a floating gate, and a control gate. The substrate has a protruding portion. The isolation feature surrounds the protruding portion of the substrate. The floating gate is over the protruding portion of the substrate, in which a sidewall of the floating gate is aligned with a sidewall of the protruding portion of the substrate. The control gate is over the floating gate.