Floating Gate Asymmetry for Semiconductor Device Coupling
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming reliable semiconductor devices at increasingly smaller sizes, as feature sizes decrease, making fabrication processes more difficult and complex.
Innovation Solution
The process involves forming isolation structures and gate structures in a semiconductor device, where the mask layer is thinned to expose portions of the isolation structures, and a gate dielectric and gate material layers are formed to create a floating gate that overlaps the isolation structures, enhancing the coupling ratio between the control gate and floating gate, thereby improving the electrical properties of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process difficulty increases and device reliability becomes harder to maintain
Solution Approach 1:
The patent applies local quality by creating a non-uniform floating gate structure where the upper portion has a greater width than the lower portion. This local variation in geometry allows the floating gate to maintain adequate coupling with the control gate even as overall device dimensions are scaled down, thereby preserving device reliability while enabling continued miniaturization for higher productivity
2Productivity
If feature sizes are decreased to increase functional density, then more devices can be packed per chip area, but fabrication process complexity increases
Solution Approach 1:
The patent employs preliminary action by forming the isolation structures with protruding edges that extend beyond the substrate surface before depositing the floating gate material. This pre-formed topography guides the subsequent conformal deposition process, ensuring that the floating gate automatically achieves the desired non-uniform width profile without requiring additional patterning steps, thus simplifying the overall fabrication process while enabling higher functional density
3Reliability
If the floating gate width is increased to enhance coupling ratio, then electrical properties are improved, but device area increases
Solution Approach 1:
The patent applies asymmetry by designing the floating gate with different widths at its upper and lower portions. The upper portion has a greater width than the lower portion, creating an asymmetric profile that maximizes the overlapping area with the control gate for enhanced coupling ratio. This asymmetric design allows the floating gate to achieve adequate electrical properties without requiring a uniform increase in overall device area, as the width expansion is localized to where it provides maximum benefit
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming a mask layer over a substrate. The method includes forming a first isolation structure and a second isolation structure passing through the mask layer and penetrating into the substrate. The method includes thinning the mask layer to expose a first portion of the first isolation structure and a second portion of the second isolation structure. The method includes partially removing the first portion, the second portion, the third portion, and the fourth portion. The method includes removing the thinned mask layer. The method includes forming a first gate over the substrate and between the first isolation structure and the second isolation structure. The method includes forming a dielectric layer over the first gate. The method includes forming a second gate over the dielectric layer and above the first gate.