Floating Gate Detection via Backward Logical Tree Analysis
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Solution Overview
Problem
Existing methods for detecting floating gates in complex electronic circuits are inefficient due to the computational intensity of analog simulation methods, which makes it difficult to identify and analyze potential floating gates, leading to missed design problems and resource wastage.
Innovation Solution
A software-based approach that works backwards from suspect gates, using logical trees and simplified digital values to determine if a gate is floating, reducing computational intensity while maintaining accuracy, and identifying the causes of floating gates to resolve the issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog simulation methods are used to detect floating gates, then measurement precision is improved, but computational intensity increases significantly
Solution Approach 1:
The patent replaces the mechanical/analog simulation process with a digital/logical system. Instead of using SPICE analog simulation to detect floating gates, the invention uses a netlist analyzer that processes circuit descriptions through logical rules and algorithms. This substitution of simulation with analysis enables precise detection without the computational intensity of full analog simulation.
Solution Approach 2:
The patent extracts only the essential information needed to detect floating gates from the complete circuit description. By using netlists and targeted logical analysis, the system extracts relevant connection data and gate terminal information without processing the entire complex circuit behavior through full simulation, thereby reducing computational requirements while maintaining detection accuracy.
2Reliability
If peer review and inspection methods are used to check circuit connections, then reliability is improved, but productivity decreases due to manual inspection time
Solution Approach 1:
The patent implements self-service through automated analysis. The netlist analyzer automatically processes circuit descriptions, applies logical rules to identify floating gates, and generates reports without requiring manual peer review. The system serves itself by autonomously detecting design problems, eliminating the need for time-consuming manual inspection while maintaining verification reliability.
Solution Approach 2:
The patent substitutes manual mechanical inspection with automated computer-based analysis. Instead of engineers manually reviewing schematics and netlists, the system uses algorithms that automatically parse circuit descriptions, apply detection rules, and identify floating gate conditions, thereby dramatically increasing productivity while maintaining or improving reliability through consistent automated verification.
Data Source
AI summary
Software method to identify which transistor gates float, and why, in complex, multi-transistor, electronic circuit designs. Transistor gates suspected of floating are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions which drive that suspect gate. The method checks if the previous level of predecessor circuit node states earlier in the circuit show up more than once with different values, thus indicating by logical conflict that a particular floating suspect gate does not float. It then repeats this back-trace analysis for the next previous level of predecessor circuit portions, further seeking logical conflicts within the expanding logic tree. This is continued until either no predecessor circuit portion that can cause the suspect gate to float is found, or until a portion that does cause the suspect gate to float is found, in which case the suspect gate is identified as a probable floating gate.